Download the IS61QDP2B42M36A1 datasheet PDF.
This datasheet also covers the IS61QDP2B44M18A variant, as both devices belong to the same 72mb quadp (burst 4) synchronous sram family and are provided as variant models within a single manufacturer datasheet.
General Description
2Mx36 and 4Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data valid window.
Separate independent read and write ports with concurrent read and write operations.
Synchronous pipeline read with late write operation.
Full PDF Text Transcription for IS61QDP2B42M36A1 (Reference)
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IS61QDP2B42M36A1. For precise diagrams, and layout, please refer to the original PDF.
IS61QDP2B44M18A/A1/A2 IS61QDP2B42M36A/A1/A2 4Mx18, 2Mx36 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM (2.0 Cycle Read Latency) DECEMBER 2014 FEATURES DESCRIPTION 2Mx36 and 4Mx...
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Cycle Read Latency) DECEMBER 2014 FEATURES DESCRIPTION 2Mx36 and 4Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window. Separate independent read and write ports with concurrent read and write operations. Synchronous pipeline read with late write operation. Double Data Rate (DDR) interface for read and write input ports. 2.0 cycle read latency. Fixed 4-bit burst for read and write operations. Clock stop support. Two input clocks (K and K#) for address and control registering at rising edges only. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data
IS61QDP2B42M36A1 Datasheet
