| Title | |
| Description | 1Mx36 and 2Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window. Separate independent read and write ports with concurrent read and write operations. Synchronous pipeline read with late write operation. Double Data Rate (DDR) interface for read and write input ports. 2.0 cycle read latency. Fixed 4-bit burst for read and write operations. Clock ... |
| Features |
DESCRIPTION
1Mx36 and 2Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window. Separate independent read and write ports with concurrent read and write operations. Synchronous pipeline read with late write operation. Double Data Rate (DDR) interface for read and write input ports. 2.0 cycle read laten... |
| Datasheet |
 IS61QDP2B451236C1 Datasheet - 858.94KB |
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