Datasheet Details
| Part number | IS61QDPB21M18A |
|---|---|
| Manufacturer | ISSI (now Infineon) |
| File Size | 600.50 KB |
| Description | 18Mb QUADP (Burst 2) Synchronous SRAM |
| Datasheet |
 IS61QDPB21M18A Datasheet
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General Description
devices.
need for high-speed bus turnaround.
operations are self-timed.
Key Features
- 512Kx36 and 1Mx18 configuration available.
- On-chip Delay-Locked Loop (DLL) for wide data valid window.
- Separate independent read and write ports with concurrent read and write operations.
- Synchronous pipeline read with EARLY write operation.
- Double Data Rate (DDR) interface for read and write input ports.
- 2.5 Cycle read latency.
- Fixed 2-bit burst for read and write operations.
- Clock stop support.
- Two input clocks (K and K#) for address and co.