Full PDF Text Transcription for IS61QDPB42M18B (Reference)
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IS61QDPB42M18B. For precise diagrams, and layout, please refer to the original PDF.
IS61QDPB42M18B/B1/B2 IS61QDPB41M36B/B1/B2 2Mx18, 1Mx36 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM (2.5 Cycle Read Latency) NOVEMBER 2014 FEATURES DESCRIPTION 1Mx36 and 2Mx18...
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cle Read Latency) NOVEMBER 2014 FEATURES DESCRIPTION 1Mx36 and 2Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window. Separate independent read and write ports with concurrent read and write operations. Synchronous pipeline read with late write operation. Double Data Rate (DDR) interface for read and write input ports. 2.5 cycle read latency. Fixed 4-bit burst for read and write operations. Clock stop support. Two input clocks (K and K#) for address and control registering at rising edges only. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
IS61QDPB42M18B Datasheet
