Datasheet4U Logo Datasheet4U.com

IS61QDPB44M18A - 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM

General Description

at page 6 for each ODT option.

The 72Mb IS61QDPB42M36A/A1/A2 and IS61QDPB44M18A/A1/A2 are synchronous, highperformance CMOS static random access memory (SRAM) devices.

These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.

Key Features

  • 2Mx36 and 4Mx18 configuration available.
  • On-chip Delay Locked Loop (DLL) for wide data valid window.
  • Separate independent read and write ports with concurrent read and write operations.
  • Synchronous pipeline read with late write operation.
  • Double Data Rate (DDR) interface for read and write input ports.
  • 2.5 cycle read latency.
  • Fixed 4-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and contr.

📥 Download Datasheet

Full PDF Text Transcription for IS61QDPB44M18A (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for IS61QDPB44M18A. For precise diagrams, and layout, please refer to the original PDF.

IS61QDPB44M18A/A1/A2 IS61QDPB42M36A/A1/A2 4Mx18, 2Mx36 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM (2.5 Cycle Read Latency) NOVEMBER 2014 FEATURES  2Mx36 and 4Mx18 configurati...

View more extracted text
cle Read Latency) NOVEMBER 2014 FEATURES  2Mx36 and 4Mx18 configuration available.  On-chip Delay Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.5 cycle read latency.  Fixed 4-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  Data Valid