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IS64LPS25636B - 9Mb Single CYCLE DESELECT STATIC RAM

Download the IS64LPS25636B datasheet PDF. This datasheet also covers the IS61LPS51218B variant, as both devices belong to the same 9mb single cycle deselect static ram family and are provided as variant models within a single manufacturer datasheet.

Description

The 9Mb product family

Features

  • Internal self-timed write cycle.
  • Individual Byte Write Control and Global Write.
  • Clock controlled, registered address, data and control.
  • Burst sequence control using MODE input.
  • Three chip enable option for simple depth ex- pansion and address pipelining.
  • Common data inputs and data outputs.
  • Auto Power-down during deselect.
  • Single cycle deselect.
  • Snooze MODE for reduced-power standby.
  • JTAG Boundary Scan.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61LPS51218B-ISSI.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
IS64LPS25618A 4Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM Integrated Silicon Solution
IS64LPS12832A 4Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM Integrated Silicon Solution
IS64LPS12836A 4Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM Integrated Silicon Solution
IS64LV51216 (IS61LV51216 / IS64LV51216) 512K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM Integrated Silicon Solution
IS64C25616AL 256K x 16 HIGH-SPEED CMOS STATIC RAM Integrated Silicon Solution

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS64LPS25636A Single CYCLE DESELECT STATIC RAM
IS64LPS25618EC SINGLE CYCLE DESELECT SRAM
IS64LPS204818B 36Mb Single CYCLE DESELECT STATIC RAM
IS64LPS102436B 36Mb Single CYCLE DESELECT STATIC RAM
IS64LPS12832EC SINGLE CYCLE DESELECT SRAM

Full PDF Text Transcription

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IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B 256K x 36, 256K x 32, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM MAY 2017 FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth ex- pansion and address pipelining • Common data inputs and data outputs • Auto Power-down during deselect • Single cycle deselect • Snooze MODE for reduced-power standby • JTAG Boundary Scan for BGA package • Power Supply LPS: Vdd 3.3V (+ 5%), Vddq 3.3V/2.5V (+ 5%) VPS: Vdd 2.5V (+ 5%), Vddq 2.5V (+ 5%) VVPS: Vdd 1.8V (+ 5%), Vddq 1.
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