IS65WV6416DBLL Datasheet | ISSI

FEATURES - High-speed access time: 35ns, 45ns, 55ns - CMOS low power operation: 15 m W (typical) operating 1.5 µW (typical) CMOS standby - TTL patible interface levels - Single power supply 1.65V--2.2V Vdd (62WV6416DALL) 2.3V--3.6V Vdd (65WV6416DBLL) - Fully static operation: no clock or refresh required - Three state outputs - Data control for upper and lower bytes - Industrial and automotive temperature support - 2CS Option Available - Lead-free available FUNCTIONAL BLOCK DIAGRAM DESCRIPTION The ISSI IS62/65WV6416DALL and IS62/65WV6416DBLL are high-speed, 1M bit static RAMs organized as 64K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields highperformance and low power consumption devices. When CS1 is HIGH (deselected) or when CS2 is LOW (deselected) or when CS1 is LOW, CS2 is HIGH and both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS62/65WV6416DALL and IS62/65WV6416DBLL are packaged in the JEDEC standard 48-pin mini BGA (6mm x 8mm) and 44-Pin TSOP (TYPE II). A0-A15 DECODER VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte CS2 CS1 OE WE UB I/O DATA CIRCUIT CONTROL CIRCUIT 64K x 16 MEMORY ARRAY COLUMN I/O Integrated Silicon Solution, Inc. - .issi. Rev. B 12/18/12 IS62WV6416DALL/DBLL IS65WV6416DALL/DBLL PIN CONFIGURATIONS 48-Pin mini BGA (6mm x 8mm) (Package Code B) 1 23 45...