IS67WVQ4M4EDBLL
Overview
- Industry Standard Serial Interface - Quad DDR (x4 xSPI) Interface: Command (1 byte) =SDR Address (2-byte) & Data = DDR - Low Signal Counts :7 Signal pins (CS#, SCLK, DQSM, SIO0~SIO3)
- High Performance - On chip ECC (chunk size = 4 bit): 1-bit correction and 2-bit detection - Double Data Rate (DDR) Operation: 200MHz (200MB/s) at 1.8V VCC (1) 133MHz (133MB/s) at 3.0V VCC - Source Synchronous Output signal during Read Operation (DQSM) - Data Mask during Write Operation (DQSM) - Configurable Latency for Read/Write Operation - Supports Variable Latency mode and Fixed Latency mode - Configurable Drive Strength - Supports Wrapped Burst mode and Continuous mode - Supports Deep Power Down mode - Hidden Refresh
- Burst Operation - Configurable Wrapped Burst Length : 16, 32, 64, and 128 - Continuous Operation: - Continues Read operation until the end of array address (No Wrapped) - Continues Write operation even after the end of array address (Wrapped to first address)
- Low Power Consumption - Single 1.7V to 1.95V Voltage Supply - Single 2.7V to 3.6V Voltage Supply - 20 mA Operating at 200MHz (1.8V, max.)
- Hardware Features - SCLK Input: Serial clock input - SIO0 - SIO3: Serial Data Input or Serial Data Output - DQSM: - Output during command, address transactions as Refresh Collision Indicator - Output during read data transactions as Read Data Strobe - Input during write data transactions as Write Data Mask - RESET#: Hardware Reset pin
- Temperature Grades - Industrial: -40°C to +85°C - Auto (A2) Grade: -40°C to +105°C
- Industry Standard PACKAGE - B = 24-ball TFBGA 6x8mm 5x5 Array - M = 16-pin 300mil SOIC(1) - KGD (Call Factory) Note: 1. 133MHz (max.) for 16-pin SOIC p
