XMC7200 Key Features
- CPU subsystem
- Single-cycle multiply
- Single/double-precision floating point unit (FPU)
- 16 KB data cache, 16 KB instruction cache
- Memory Protection Unit (MPU)
- 16 KB instruction and 16-KB data tightly-coupled memories (TCM)
- Single-cycle multiply
- Memory Protection Unit
- Inter-processor munication in hardware
- Three DMA controllers