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Infineon Technologies Electronic Components Datasheet

05N03LAG Datasheet

IPU05N03LAG

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05N03LAG pdf
OptiMOS®2 Power-Transistor
Features
• Ideal for high-frequency dc/dc converters
• Qualified according to JEDEC1) for target application
• N-channel, logic level
• Excellent gate charge x R DS(on) product (FOM)
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• Superior thermal resistance
• 175 °C operating temperature
• Pb-free lead plating; RoHS compliant
IPD05N03LA G IPF05N03LA G
IPS05N03LA G IPU05N03LA G
Product Summary
V DS
R DS(on),max (SMD version)
ID
25 V
5.1 m
50 A
Type
Type
IPD05N03LA
IPF05N03LA
IPPaSc0k5aNg0e3LA
IMPaUr0k5inNg03LA
IPD05N03LA
IPF05N03LA
Package
Ordering Code
P-TO252-3-11 Q67042-S4144
P-TO252-3-23 Q67042-S
P-TOP2-5T2O-32-5111-3-11 P-QT6O7205422--3S-23
05N0P3-LTAO251-3-21 05QN60730L4A2-S4230
IPS05N03LA
Marking
05N03LA
05N03LA
05PN-T0O3L2A51-3-11
050N5N030L3ALA
IPU05N03LA
P-TO251-3-1
05N03LA
Maximum ratings, at T j=25 °C, unless otherwise specified
Parameter
Symbol Conditions
Continuous drain current
I D T C=25 °C2)
T C=100 °C
Pulsed drain current
I D,pulse T C=25 °C3)
Avalanche energy, single pulse
E AS I D=45 A, R GS=25
Reverse diode dv /dt
dv /dt
I D=50 A, V DS=20 V,
di /dt =200 A/µs,
T j,max=175 °C
Gate source voltage4)
V GS
Power dissipation
P tot T C=25 °C
Operating and storage temperature T j, T stg
IEC climatic category; DIN IEC 68-1
Value
50
50
350
300
6
±20
94
-55 ... 175
55/175/56
Unit
A
mJ
kV/µs
V
W
°C
Rev. 2.0
page 1
2006-05-11


Infineon Technologies Electronic Components Datasheet

05N03LAG Datasheet

IPU05N03LAG

No Preview Available !

05N03LAG pdf
IPD05N03LA G IPF05N03LA G
IPS05N03LA G IPU05N03LA G
Parameter
Symbol Conditions
min.
Values
typ.
Unit
max.
Thermal characteristics
Thermal resistance, junction - case
SMD version, device on PCB
R thJC
R thJA
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minimal footprint
6 cm2 cooling area5)
-
-
-
- 1.6 K/W
- 75
- 50
Electrical characteristics, at T j=25 °C, unless otherwise specified
Static characteristics
Drain-source breakdown voltage
Gate threshold voltage
Zero gate voltage drain current
V (BR)DSS V GS=0 V, I D=1 mA
V GS(th) V DS=V GS, I D=50 µA
I DSS
V DS=25 V, V GS=0 V,
T j=25 °C
25
1.2
-
-
1.6
0.1
-V
2
1 µA
Gate-source leakage current
Drain-source on-state resistance
Gate resistance
Transconductance
V DS=25 V, V GS=0 V,
T j=125 °C
I GSS
R DS(on)
V GS=20 V, V DS=0 V
V GS=4.5 V, I D=30 A
V GS=4.5 V, I D=30 A,
SMD version
V GS=10 V, I D=30 A
V GS=10 V, I D=30 A,
SMD version
RG
g fs
|V DS|>2|I D|R DS(on)max,
I D=30 A
-
-
-
-
-
-
-
31
10 100
10 100 nA
6.9 8.6 m
6.7 8.4
4.4 5.3
4.2 5.1
1 -
62 - S
1) J-STD20 and JESD22
2) Current is limited by bondwire; with an R thJC=1.6 K/W the chip is able to carry 106 A.
3) See figure 3
4) T j,max=150 °C and duty cycle D <0.25 for V GS<-5 V
5) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
Rev. 2.0
page 2
2006-05-11


Part Number 05N03LAG
Description IPU05N03LAG
Maker Infineon Technologies
Total Page 12 Pages
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