PMB9500
Overview
- Supports 3GPP release 99 and release 4 physical channel processing requirements Data-rate scalable channel elements across all spreading factors Up to 64 uplink channel elements supporting a variety of receiver structures - Pool of 384 fingers, configurable as 6-16 finger RAKE receivers 9600 MOPS 16-bit embedded dataflow DSP array 96 multipath searchers 4096-tap access channel preamble detection engine 384 downlink channel resources Supports up to 12 uplink and downlink antenna ports Object-oriented ANSI-C application programming interface for runtime configuration, management and control - Virtual machine interface (VMI) Embedded firmware development tools for customer proprietary radio link, power control and measurement algorithms Embedded firmware library of 3GPP reference algorithms - Channel estimation - Delayed-locked loop - Frequency-locked loop - RSCP estimation - ISCP estimation - UL and DL power control - Pilot BER measurement - Tx code-power measurement - Power-delay profile measurement Type 3G Basestation Processor Sales Code CBME V1.1 - PMB 9500 Package P-EBGA-600 Wireless Communication morphICs Infineon T
