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IA8237 Datasheet Preview

IA8237 Datasheet

Programmable DMA Controller

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IA8237 pdf
IA8237
Programmable DMA Controller
Page 1 of 4
Advanced Information Sheet
FEATURES
Form, Fit, and Function Compatible with the Intel® 8237A and Harris©
82C37A
Packaging options available: 40 Pin Plastic Dip or 44 Pin Plastic Leaded
Chip Carrier
Static Read/Write or Handshaking Modes
Direct Bit Set/Reset Capability
Memory-to-Memory Transfers
The IA8237 uses innovASIC’s innovative new f 3 Program to provide industry with parts that
other vendors have declared obsolete. By specifying parts through this program a customer is
assured of never having a component become obsolete again. This advanced information sheet
assumes the original part has been designed in, and so provides a summary of capabilities only. For
new designs contact innovASIC for more detailed information.
Intel is a registered trademark of Intel Corporation
Harris is a copyright trademark of Harris Corporation
IOR_n
IOW_n
MEMR_n
MEMW_n
N. C.
READY
HLDA
ADSTB
AEN
HRQ
CS_n
CLK
RESET
DACK2
DACK3
DREQ3
DREQ2
DREQ1
DREQ0
VSS
(1) IA8237
(2) 40 Pin DIP
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(40)
(39)
(38)
(37)
(36)
(35)
(34)
(33)
(32)
(31)
(30)
(29)
(28)
(27)
(26)
(25)
(24)
(23)
(22)
(21)
Package Pinout
A7
A6
A5
A4
EOP_n
A3
A2
A1
A0
VCC
DB0
DB1
DB2
DB3
DB4
DACK0
DACK1
DB5
DB6
DB7
N. C.
N. C.
HLDA
ADSTB
AEN
HRQ
CS_n
CLK
RESET
DACK2
N. C.
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
IA8237
44 Pin LCC
(39) A3
(38) A2
(37) A1
(36) A0
(35) VCC
(34) DB0
(33) DB1
(32) DB2
(31) DB3
(30) DB4
(29) N. C.
Copyright © 1999, InnovASIC Inc.
Customer Specific IC Solutions



InnovASIC
InnovASIC

IA8237 Datasheet Preview

IA8237 Datasheet

Programmable DMA Controller

No Preview Available !

IA8237 pdf
IA8237
Programmable DMA Controller
Page 2 of 4
Advanced Information Sheet
The IA8237 is a programmable direct memory access (DMA) mega-function designed to be
functionally equivalent to the Intel 8237A and Harris 82C37A devices. The A8237 controls data
transfers between memory and peripherals, memory-to-memory transfers, and block memory
initialization. Four independently programmable channels are available, and requests may be
generated via hardware or software.
A block diagram is shown in Figure 1.
Functional Block Diagram
Figure 1
EOP_n
RESET
CS_n
READY
CLK
AEN
ADSTB
MEMR_n
MEMW_n
IOR_n
IOW_n
TIMING
AND
CONTROL
DREQ0_n :
DREQ3_n
HDLA
HRQ_n
DACK0 :
DACK3
PRIORITY
ENCODER
AND
ROTATING
PRIORITY
LOGIC
DECREMENTOR
TEMP WORD
COUNT REG
INC/DECREMENTOR
TEMP ADDRESS
REG
IO
BUFFER
A0 : A3
16
READ BUFFER
16
READ WRITE BUFFER
BASE
ADDRESS
BASE
WORD
COUNT
CURRENT
ADDRESS
CURRENT
WORD
COUNT
COMMAND
WRITE
BUFFER
READ
BUFFER
INTERNAL DATA
BUS
OUTPUT
BUFFER
A4 : A7
COMMAND
CONTROL
IO
BUFFER
DB0 : DB7
MASK
REQUEST
READ
WRITE
STATUS
TEMPORARY
MODE
Copyright © 1999, InnovASIC Inc.
Customer Specific IC Solutions


Part Number IA8237
Description Programmable DMA Controller
Maker InnovASIC
Total Page 4 Pages
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