NDT28P - 2Gb (x8) DDR3L Synchronous DRAM

Datasheet Details

including full backward compatibility to DDR3. Hereafter the device will be referred to as DDR3L for both part numbers. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with differential DQS pair in a source synchronous fashion. These devices operate with a single +1.35V -0.067V / +0.1V power supply and are available in.

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Published: May 16, 2019 |