Datasheet4U Logo Datasheet4U.com

ICS527-03 - Clock Slicer User Configurable PECL Output Zero Delay Buffer

Description

The ICS527-03 is the most flexible way to generate an output clock from an input clock with zero skew.

The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock.

The part supports non-integer multiplications and divisions.

Features

  • Packaged as 28 pin SSOP (150 mil body) Synchronizes fractional clocks rising edges CMOS in to PECL out Pin selectable dividers Zero input to output skew User determines the output frequency - no software needed Slices frequency or period Input clock frequency of 1.5 MHz to 200 MHz Output clock frequencies from 2.5 MHz to 160 MHz Very low jitter Duty cycle of 45/55 Ope.

📥 Download Datasheet

Datasheet Details

Part number ICS527-03
Manufacturer Integrated Circuit Systems
File Size 200.47 KB
Description Clock Slicer User Configurable PECL Output Zero Delay Buffer
Datasheet download datasheet ICS527-03 Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
ICS527-03 CLOCK SLICER USER CONFIGURABLE PECL OUTPUT ZDB Renesas
ICS527-02 CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER Renesas
ICS527-04 Clock Slicer Renesas
ICS524 LOW SKEW 1 TO 4 CLOCK BUFFER Integrated Device Technology
ICS524 LOW SKEW 1 TO 4 CLOCK BUFFER Renesas

Other Datasheets by Integrated Circuit Systems

Part Number Description
ICS527-01 User Configurable Zero Delay Buffer
ICS527-02 Clock Slicer User Configurable PECL Input Zero Delay Buffer
ICS527-04 Clock Slicer User Configurable PECL input Zero Delay Buffer
ICS525-01 (ICS525-01/02) User Configurable Clock
ICS525-02 (ICS525-01/02) User Configurable Clock

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com Preliminary Information ICS527-03 Clock Slicer User Configurable PECL Output Zero Delay Buffer Description The ICS527-03 is the most flexible way to generate an output clock from an input clock with zero skew. The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock. The part supports non-integer multiplications and divisions. Using Phase-Locked Loop (PLL) techniques, the device accepts an input clock up to 200 MHz and produces an output clock up to 160 MHz. The ICS527-03 aligns rising edges on CLKIN with FBPECL at a ratio determined by the reference and feedback dividers. For a PECL input and output clock with zero delay, use the ICS527-04.
Published: |