system peripheral clock source.
* Packaged in 20 pin tiny SSOP (QSOP) ª Operating VDD of 3.3V or 5V
* Less than one ppm synthesis error in all clocks
* Inexpensive 14.31818 MHz crystal or cl.
Using analog/digital Phase-Locked Loop (PLL) techniques, the device accepts a parallel resonant 14.31818 MHz crystal in.
The ICS650-01B is a low cost, low jitter, high performance clock synthesizer for system peripheral applications. Using analog/digital Phase-Locked Loop (PLL) techniques, the device accepts a parallel resonant 14.31818 MHz crystal input to produce up .
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