system peripheral clock source.
* Packaged in 20 pin tiny SSOP (QSOP)
* Lower jitter version of ICS650-01
* Operating VDD of 3.3V or 5V
* Zero ppm synthesis error in all clocks
* Ine.
Using analog/digital Phase-Locked Loop (PLL) techniques, the device accepts a parallel resonant 25 MHz crystal input to.
The ICS650-21 is a low cost, low jitter, high performance clock synthesizer for system peripheral applications. Using analog/digital Phase-Locked Loop (PLL) techniques, the device accepts a parallel resonant 25 MHz crystal input to produce up to eigh.
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