Datasheet4U Logo Datasheet4U.com

ICS8735-21 - ZERO DELAY CLOCK GENERATOR

General Description

The ICS8735-21 is a highly versatile 1:1 Differential-to-3.3V LVPECL clock generator and a HiPerClockS™ member of the HiPerClockS™family of High Performance Clock Solutions from ICS.

The CLK, nCLK pair can accept most standard differential input levels.

Key Features

  • 1 differential 3.3V LVPECL output pair, 1 differential feedback output pair.
  • Differential CLK, nCLK input pair.
  • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL.
  • Output frequency range: 31.25MHz to 700MHz.
  • Input frequency range: 31.25MHz to 700MHz.
  • VCO range: 250MHz to 700MHz.
  • Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:.

📥 Download Datasheet

Datasheet Details

Part number ICS8735-21
Manufacturer Integrated Circuit Systems
File Size 198.64 KB
Description ZERO DELAY CLOCK GENERATOR
Datasheet download datasheet ICS8735-21 Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
ICS8735I-21 ZERO DELAY CLOCK GENERATOR IDT
ICS873032 5V LVPECL/ECL CLOCK GENERATOR Integrated Circuit System
ICS873034 3.3V LVPECL/ECL CLOCK GENERATOR Integrated Circuit System
ICS873991-147 LOW VOLTAGE LVCMOS/LVPECL-TO LVPECL/ECL CLOCK GENERATOR Integrated Device Technology
ICS873991-147 LOW VOLTAGE LVCMOS/LVPECL-TO LVPECL/ECL CLOCK GENERATOR Integrated Device Technology

Other Datasheets by Integrated Circuit Systems

Part Number Description
ICS8735-01 ZERO DELAY CLOCK GENERATOR
ICS87354I CLOCK GENERATOR
ICS873033 3.3V 5V LVPECL/ECL CLOCK GENERATOR
ICS873033 HIGH SPEED 4 DIFFERENTIAL-TO- 3.3V 5V LVPECL/ECL CLOCK GENERATOR
ICS8737-11 CLOCK GENERATOR

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Integrated Circuit Systems, Inc. ICS8735-21 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR FEATURES • 1 differential 3.3V LVPECL output pair, 1 differential feedback output pair • Differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Output frequency range: 31.25MHz to 700MHz • Input frequency range: 31.25MHz to 700MHz • VCO range: 250MHz to 700MHz • Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 • External feedback for “zero delay” clock regeneration with configurable frequencies • Cycle-to-cycle jitter: 25ps (maximum) • Static phase offset: 50ps ± 100ps • 3.