ICS9147-09 Datasheet PDF - Integrated Circuit Systems Frequency Generator & Integrated Buffers Specs

ICS9147-09 - Frequency Generator & Integrated Buffers

Datasheet Summary

Description

The ICS9147-09 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro,AMD or Cyrix processors.

Four bidirectional I/O pins (FS0, FS1, FS2, BSEL) are latched at power-on to the functionality table.

Features

Total of 15 CPU speed clocks: - Two copies of CPU clock with VDDL (2.5 to 3.3V) - Twelve (12) SDRAM (3.3v) plus one CPUH/AGP (3.3V) clocks Six copies of BUS clock (synchronous with CPU clock/2 or asynchronous 32 MHz) 250ps output skew window for CPU andSDRAM clocks and 500ps window BUS clocks. CPU clocks to BUSclocks skew 1-4ns (CPU early) Two copies of Ref. clock @14.31818 MHz (One driven by VDDL as IOAPIC) One 48 MHz (3.3 V TTL) for USB support and single 24 MHz. Separate VDDL for CPUL (1:2).

Datasheet Details

Part number	ICS9147-09
Manufacturer	Integrated Circuit Systems
File Size	601.92 KB
Description	Frequency Generator & Integrated Buffers
Datasheet	ICS9147-09 Datasheet
Additional preview pages of the ICS9147-09 datasheet.

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Full PDF Text Transcription

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Integrated Circuit Systems, Inc. ICS9147-09 Frequency Generator & Integrated Buffers for 686 Series CPUs General Description The ICS9147-09 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro,AMD or Cyrix processors. Four bidirectional I/O pins (FS0, FS1, FS2, BSEL) are latched at power-on to the functionality table. The Six BUS clocks can be selected as either synchronous at 1/2 CPU speed or asynchronous at 32MHz selected by BSEL latched input.The inputs provide for tristate and test mode conditions to aid in system level testing.These multiplying factors can be customized for specific applications. Glitch-free stop clock controls provided for CPU.

Published: Feb 6, 2006 |