ICS93732 Datasheet PDF (Low Cost DDR Phase Lock Loop Zero Delay Buffer) | Download Integrated Circuit Systems ICS93732

ICS93732 - Low Cost DDR Phase Lock Loop Zero Delay Buffer

Features

Low skew, low jitter PLL clock driver.
Max frequency supported = 266MHz (DDR 533).
I2C for functional and output control.
Feedback pins for input to output synchronization.
Spread Spectrum tolerant inputs.
3.3V tolerant CLK_INT input Switching Characteristics:.
CYCLE - CYCLE jitter (66MHz): 100MHz): 200MHz):.

Datasheet Details

Part number	ICS93732
Manufacturer	Integrated Circuit Systems
File Size	475.15 KB
Description	Low Cost DDR Phase Lock Loop Zero Delay Buffer
Datasheet	ICS93732 Datasheet

📁 Similar Datasheet

ICS93732 - Low Cost DDR Phase Lock Loop Zero Delay Buffer (Renesas)

ICS93705 - DDR Phase Lock Loop Zero Delay Clock Buffer (Renesas)

ICS932S203 - Frequency Generator (IDT)

ICS932S208 - Programmable Timing Control Hub (IDT)

ICS932S421B - PCIe Gen2 and QPI Clock (IDT)

ICS932S801 - K8 Clock Chip (ICS)

ICS932S805C - K8 Clock Chip (IDT)

ICS9341 - 133MHz Clock Generator and Integrated Buffer (Renesas)

ICS90C64 - Dual Video/Memory Clock Generator (Western Digital)

ICS9112-26 - Low Skew Output Buffer (Renesas)

Full PDF Text Transcription

Click to expand full text

Integrated Circuit Systems, Inc. ICS9373 2 Low Cost DDR Phase Lock Loop Zero Delay Buffer Recommended Application: DDR Zero Delay Clock Buffer Product Description/Features: • Low skew, low jitter PLL clock driver • Max frequency supported = 266MHz (DDR 533) • I2C for functional and output control • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • 3.3V tolerant CLK_INT input Switching Characteristics: • CYCLE - CYCLE jitter (66MHz): <120ps • CYCLE - CYCLE jitter (>100MHz): <65ps • CYCLE - CYCLE jitter (>200MHz): <75ps • OUTPUT - OUTPUT skew: <100ps • DUTY CYCLE: 49.5% - 50.

Published: Mar 18, 2015 |