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Integrated Circuit Systems

ICS94201 Datasheet Preview

ICS94201 Datasheet

Programmable System Frequency Generator

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Integrated
Circuit
Systems, Inc.
ICS94201
Programmable System Frequency Generator for PII/III
Recommended Application:
810/810E and Solano (815) type chipset
Output Features:
• 2 - CPUs @ 2.5V
• 13 - SDRAM @ 3.3V
• 3 - 3V66 @ 3.3V
• 8 - PCI @3.3V
• 1 - 24/48MHz@ 3.3V
• 1 - 48MHz @ 3.3V fixed
• 1 - REF @3.3V, 14.318MHz
Features:
• Programmable ouput frequency.
• Programmable ouput rise/fall time for PCI
and SDRAM clocks.
• Programmable 3V66 to PCI skew.
• Spread spectrum for EMI control
with programmable spread percentage.
• Watchdog timer technology to reset system
if over-clocking causes malfunction.
• Support power management through PD#.
• Uses external 14.318MHz crystal.
• FS pins for frequency select
Key Specifications:
• CPU Output Jitter: <250ps
• IOAPIC Output Jitter: <500ps
• 48MHz, 3V66, PCI Output Jitter: <500ps
• CPU Output Skew: <175ps
• PCI Output Skew: <500ps
• 3V66 Output Skew <175ps
• For group skew timing, please refer to the
Group Timing Relationship Table.
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Pin Configuration
VDDREF
X1
X2
GNDREF
GND3V66
3V66-0
3V66-1
3V66-2
VDD3V66
VDDPCI
1*(FS0)PCICLK0
1*(FS1)PCICLK1
1*(SEL24_48#)PCICLK2
GNDPCI
PCICLK3
PCICLK4
PCICLK5
VDDPCI
PCICLK6
PCICLK7
GNDPCI
PD#
SCLK
SDATA
VDDSDR
SDRAM11
SDRAM10
GNDSDR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 REF0(FS4)*1
55 VDDLAPIC
54 IOAPIC
53 VDDLCPU
52 CPUCLK0
51 CPUCLK1
50 GNDLCPU
49 GNDSDR
48 SDRAM0
47 SDRAM1
46 SDRAM2
45 VDDSDR
44 SDRAM3
43 SDRAM4
42 SDRAM5
41 GNDSDR
40 SDRAM6
39 SDRAM7
38 SDRAM_F
37 VDDSDR
36 GND48
35 24_48MHz(FS2)*
34 48MHz(FS3)*1
33 VDD48
32 VDDSDR
31 SDRAM8
30 SDRAM9
29 GNDSDR
56-Pin 300 mil SSOP
1. These pins will have 1.5 to 2X drive strength.
* 120K ohm pull-up to VDD on indicated inputs.
Block Diagram
PLL2
X1 XTAL
X2 OSC
PLL1
Spread
Spectrum
FS[4:0]
PD#
SEL24_48#
SDATA
SCLK
Control
Logic
Config.
Reg.
/2
CPU
DIVDER
SDRAM
DIVDER
IOAPIC
DIVDER
PCI
DIVDER
3V66
DIVDER
48MHz
24_48MHz
REF0
2 CPUCLK [1:0]
12 SDRAM [11:0]
SDRAM_F
IOAPIC
PCICLK [7:0]
8
3V66 [2:0]
3
94201 Rev A - 05/24/01
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.




Integrated Circuit Systems

ICS94201 Datasheet Preview

ICS94201 Datasheet

Programmable System Frequency Generator

No Preview Available !

www.DataSheet4U.com
ICS94201
General Description
The ICS94201 is a single chip clock solution for desktop designs using the 810/810E and Solano style chipset. It provides all necessary
clock signals for such a system.
The ICS94201 belongs to ICS new generation of programmable system clock generators. It employs serial programming I2C interface
as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to output skew,
changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocks. This device also has ICS
propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system become unstable from over
clocking.
Spread spectrum typically reduces system EMI by 7dB to 8dB. This simplifies EMI qualification without resorting to board design
iterations or costly shielding.
Pin Configuration
PIN
N UM B ER
PIN NAM E
1, 9, 10, 18, 25,
32, 33, 37, 45
VDD
2 X1
3
4, 5, 14, 21,
28, 29, 36,
41, 49
8, 7, 6
11
12
X2
GND
3V66 [2:0]
PCICLK01
FS0
PCICLK11
FS1
TYPE
D ES CR IPTION
PWR
IN
OUT
3.3V power supply
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
PWR Ground pins for 3.3V supply
OUT
OUT
IN
OUT
IN
3.3V Fixed 66MHz clock outputs for HUB
3.3V PCI clock output, with Synchronous CPUCLKs
Logic input frequency select bit. Input latched at power on.
3.3V PCI clock output, with Synchronous CPUCLKs
Logic input frequency select bit. Input latched at power on.
13
20, 19, 17,
16, 15
SEL_24_48#
PCICLK21
PCICLK [7:3]
IN
OUT
OUT
22 PD#
IN
23 SCLK
IN
24 SDATA
OUT
FS3
34
48MHz
IN
OUT
35
38
48, 47, 46, 44,
43, 42, 40, 39,
31, 30, 27, 26
FS2
24_48MHz
SDRAM_F
SDRAM [11:0]
IN
OUT
OUT
OUT
50 GNDL
PWR
51, 52
CPUCLK [1:0] OUT
53, 55
VDDL
PWR
www54.DataISOAhPeICet4U.coOmUT
56
FS4
REF01
IN
OUT
Logic input to select output.
3.3V PCI clock output, with Synchronous CPUCLKs
3.3V PCI clock outputs, with Synchronous CPUCLKs
Asynchronous active low input pin used to power down the device into a
low power state. The internal clocks are disabled and the VCO and the
crystal are stopped. The latency of the power down will not be greater
than 3ms.
Clock input of I2C input
Data input for I2C serial input.
Logic input frequency select bit. Input latched at power on.
3.3V Fixed 48MHz clock output for USB
Logic input frequency select bit. Input latched at power on.
3.3V 24_48MHz output, selectable through pin 13, default is 24MHz.
3.3V SDRAM output can be turned off through I2C
3.3V output. All SDRAM outputs can be turned off through I2C
Ground for 2.5V power supply for CPU & APIC
2.5V Host bus clock output. Output frequency derived from FS pins.
2.5V power suypply for CPU, IOAPIC
2.5V clock outputs running at 16.67MHz.
Logic input frequency select bit. Input latched at power on.
3.3V, 14.318MHz reference clock output.
2



Part Number ICS94201
Description Programmable System Frequency Generator
Maker Integrated Circuit Systems
Total Page 18 Pages
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ICS94201 Datasheet PDF





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