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Integrated Circuit Systems

ICS952607 Datasheet Preview

ICS952607 Datasheet

Programmable Timing Control Hub for Next Gen P4 processor

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Integrated
Circuit
Systems, Inc.
ICS952607
Advance Information
Programmable Timing Control Hub™ for Next Gen P4™ processor
Recommended Application:
CK409 Compliant clock for Next Gen P4 Processor
Output Features:
• 2 - 0.7V current-mode differential CPU pairs
• 1 - 0.7V current-mode differential SRC pair
• 9 - PCI, 3 free running, 33MHz
• 3 - REF, 14.318MHz
• 3 - 3V66, 66.66MHz
• 1 - VCH/3V66, selectable 48MHz or 66MHz
• 2 - 48MHz
• 1 - 24/48MHz
Key Specifications:
• CPU/SRC outputs cycle-cycle jitter < 125ps
• 3V66 outputs cycle-cycle jitter < 250ps
• PCI outputs cycle-cycle jitter < 250ps
• +/- 300ppm frequency accuracy on CPU & SRC clocks
Features/Benefits:
• QuadRomTM frequency selection.
• Programmable output frequency.
• Programmable asynchronous 3V66&PCI frequency.
• Programmable output divider ratios.
• Programmable output rise/fall time.
• Programmable output skew.
• Programmable spread percentage for EMI control.
• Watchdog timer technology to reset system if system
malfunctions.
• Programmable watch dog safe frequency.
• Support I2C Index read/write and block read/write
operations.
• Uses external 14.318MHz reference input.
• Supports tight ppm accuracy clocks for Serial-ATA
• Supports spread spectrum modulation, 0 to -0.5%
down spread and +/- 0.25% center spread
• Supports CPU clks up to 400MHz
Functionality
Bit4 Bit3 Bit2 Bit1 Bit0
FS4 FS3 FS2 FS1 FS0
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
CPU
MHz
100.00
200.00
133.33
166.67
200.00
400.00
266.67
333.33
100.99
201.98
134.65
168.31
115.00
230.00
153.33
191.67
100.00
200.00
133.33
166.67
200.00
400.00
266.67
333.33
105.00
210.00
140.00
175.00
110.00
220.00
146.66
183.34
0734—07/16/04
AGP
MHz
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
67.33
67.33
67.33
67.32
76.66
76.66
76.66
76.66
66.66
66.66
66.66
71.43
66.66
66.66
66.66
66.66
69.99
69.99
69.99
69.99
73.33
73.33
73.33
73.33
PCI
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.66
33.66
33.66
33.66
38.33
38.33
38.33
38.33
33.33
33.33
33.33
35.71
33.33
33.33
33.33
33.33
35.00
35.00
35.00
35.00
36.66
36.66
36.66
36.66
Pin Configuration
*FS1/REF0
*FS0/REF1
REF2
VDDREF
X1
X2
GND
**FS2/PCICLK_F0
**FS4/PCICLK_F1
1
2
3
4
5
6
7
8
9
48 VDDA
47 GND
46 IREF
45 Reset#
44 GND
43 CPUCLKT1
42 CPUCLKC1
41 VDDCPU
40 CPUCLKT0
PCICLK_F2 10
VDDPCI 11
GND 12
^^PCICLK0 13
PCICLK1 14
PCICLK2 15
PCICLK3 16
VDDPCI 17
GND 18
PCICLK4 19
PCICLK5 20
**Sel24_48#/24_48MHz 21
**FS3/48MHz_0 22
48MHz_1 23
GND 24
39 CPUCLKC0
38 GND
37 SRCCLKT
36 SRCCLKC
35 VDD
34 VttPWR_GD/PD#
33 SDATA
32 SCLK
31 3V66_0
30 3V66_1
29 GND
28 VDD3V66
27 3V66_2
26 3V66_3/VCH
25 VDD48
* This pin have 120K pull-up to VDD
** This pin have 120K pull-down to GND
^^ An external 2.2K pull-down resistor is needed on this pin
48-pin SSOP
Note: FS1 and FS0 are equal to Intel CK409-defined FSA and FSB,
respectively.
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.




Integrated Circuit Systems

ICS952607 Datasheet Preview

ICS952607 Datasheet

Programmable Timing Control Hub for Next Gen P4 processor

No Preview Available !

Integrated
Circuit
Systems, Inc.
ICS952607
Advance Information
Pin Description
PIN
#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIN NAME
*FS1/REF0
*FS0/REF1
REF2
VDDREF
X1
X2
GND
**FS2/PCICLK_F0
**FS4/PCICLK_F1
PCICLK_F2
VDDPCI
GND
^^PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
21 **Sel24_48#/24_48MHz
22 **FS3/48MHz_0
23 48MHz_1
24 GND
25 VDD48
26 3V66_3/VCH
27 3V66_2
28 VDD3V66
29 GND
30 3V66_1
31 3V66_0
32 SCLK
33 SDATA
PIN TYPE DESCRIPTION
I/O
I/O
OUT
PWR
IN
OUT
PWR
I/O
I/O
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
I/O
I/O
OUT
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
IN
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
14.318 MHz reference clock.
Ref, XTAL power supply, nominal 3.3V
Crystal input,nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
Frequency select latch input pin / 3.3V PCI free running clock output.
Frequency select latch input pin / 3.3V PCI free running clock output.
Free running PCI clock not affected by PCI_STOP# .
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
Latched select input for 24/48MHz output / 24/48MHz clock output. 1=24mHz, 0 =
48MHz.
Frequency select latch input pin / Fixed 48MHz clock output. 3.3V
48MHz clock output.
Ground pin.
Power for 24 & 48MHz output buffers and fixed PLL core.
3.3V 66.66MHz clock output / 48MHz VCH clock output.
3.3V 66.66MHz clock output
Power pin for the 3V66 clocks.
Ground pin.
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
Clock pin of I2C circuitry 5V tolerant
Data pin for I2C circuitry 5V tolerant
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs
34 VttPWR_GD/PD# IN are valid and are ready to be sampled. This is an active high input. / Asynchronous
active low input pin used to power down the device into a low power state.
35 VDD
36 SRCCLKC
37 SRCCLKT
38 GND
39 CPUCLKC0
40 CPUCLKT0
41 VDDCPU
42 CPUCLKC1
43 CPUCLKT1
44 GND
45 Reset#
46 IREF
47 GND
48 VDDA
PWR
OUT
OUT
PWR
OUT
OUT
PWR
OUT
OUT
PWR
OUT
OUT
PWR
PWR
Power supply, nominal 3.3V
Complement clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
Ground pin.
"Complementary" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
"Complementary" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Ground pin.
Real time system reset signal for frequency gear ratio change or watchdog timer
timeout. This signal is active low.
This pin establishes the reference current for the CPUCLK pairs. This pin requires a
fixed precision resistor tied to ground in order to establish the appropriate current.
Ground pin.
3.3V power for the PLL core.
0734—07/16/04
2


Part Number ICS952607
Description Programmable Timing Control Hub for Next Gen P4 processor
Maker Integrated Circuit Systems
Total Page 21 Pages
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