* Low skew, low jitter PLL clock driver
* 1 to 13 differential clock distribution (SSTL_2)
* Feedback pins for input to output synchronization
* PD# for power management
* Spread Spectrum-tolerant inputs
* Auto PD when input signal removed
ICS95V860 Datasheet (107.59 KB)
ICS95V860
Integrated Circuit Systems
107.59 KB
2.5v ddr/zero delay fan out buffer.
Integrated Circuit Systems, Inc. ICS95V860 2.5V DDR/Zero Delay Fan Out Buffer (100MHz - 225MHz) Recommended Application: DDR Memory Modules / Zero D.
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