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ICS9FG108 - Programmable FTG for Differential P4 CPU

Description

PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PIN NAME XIN/CLKIN X2 VDD GND REFOUT FS2 OE_7 DIF_7 DIF_7# VDD DIF_6 DIF_6# OE_6 VDD GND OE_5 DIF_5 DIF_5# VDD DIF_4 DIF_4# OE_4 SDATA SCLK PIN TYPE IN OUT PWR PWR OUT IN IN OUT OUT PWR OUT OUT IN PWR

Features

  • Generates common frequencies from 14.318 MHz or 25 MHz.
  • Crystal or reference input.
  • 8 - 0.7V current-mode differential output pairs.
  • Supports Serial-ATA at 100 MHz.
  • Two spread spectrum modes: 0 to -0.5 downspread and +/-0.25% centerspread.
  • Unused inputs may be disabled in either driven or HiZ state for power management.
  • Programmable OE Polarity.
  • M/N Programming Key Specifications:.
  • Output cycle-to-cycle jitter <.

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Datasheet Details

Part number ICS9FG108
Manufacturer Integrated Circuit Systems
File Size 218.58 KB
Description Programmable FTG for Differential P4 CPU
Datasheet download datasheet ICS9FG108 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS9FG108 Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks Recommended Application: Pin Configuration XIN/CLKIN X2 VDD GND REFOUT FS2 OE_7** DIF_7 DIF_7# VDD DIF_6 DIF_6# OE_6* VDD GND OE_5* DIF_5 DIF_5# VDD DIF_4 DIF_4# OE_4** SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDA GNDA IREF FS0 FS1 OE_0** DIF_0 DIF_0# VDD DIF_1 DIF_1# OE_1* VDD GND OE_2* DIF_2 DIF_2# VDD DIF_3 DIF_3# OE_3** SEL14M_25M# SPREAD DIF_STOP# Frequency Timing Generator for Differential CPU, PCIExpress & SATA clocks Features: • Generates common frequencies from 14.318 MHz or 25 MHz • Crystal or reference input • 8 - 0.
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