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IDT74LVC125A Datasheet

3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O

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IDT74LVC125A
3.3VCMOSQUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
3.3V CMOS QUADRUPLE
BUS BUFFER GATE
WITH 3-STATE OUTPUTS
AND 5 VOLT TOLERANT I/O
INDUSTRIALTEMPERATURERANGE
IDT74LVC125A
FEATURES:
• 0.5 MICRON CMOS Technology
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• All inputs, outputs, and I/Os are 5V tolerant
• Supports hot insertion
• Available in SOIC, SSOP, and TSSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
DESCRIPTION:
The LVC125A quadruple bus buffer gate is built using advanced dual
metal CMOS technology. The LVC125A features independent line drivers
with 3-state outputs. Each output is disabled when the associated output-
enable (OE) input is high.
To ensure the high impedance state during power up or power down,
OE should be tied to Vcc through a pullup resistor; the minimum value of the
resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V system environment.
The LVC125A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
1OE
1
2
1A
2OE 4
5
2A
3
1Y
6 2Y
3OE
10
9
3A
4OE 13
12
4A
8
3Y
11 4Y
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
©2000 Integrated Device Technology, Inc.
1
FEBRUARY 2000
DSC-4557/1


Integrated Device Technology Electronic Components Datasheet

IDT74LVC125A Datasheet

3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O

No Preview Available !

IDT74LVC125A
3.3VCMOSQUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
INDUSTRIALTEMPERATURERANGE
PIN CONFIGURATION
1OE
1A
1Y
2OE
2A
2Y
GND
1
2
3
4
5
6
7
14 VCC
13 4OE
12 4A
11 4Y
10 3OE
9 3A
8 3Y
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max
VTERM Terminal Voltage with Respect to GND –0.5 to +6.5
TSTG Storage Temperature
–65 to +150
IOUT DC Output Current
–50 to +50
IIK Continuous Clamp Current,
IOK VI < 0 or VO < 0
–50
ICC Continuous Current through each
ISS VCC or GND
±100
Unit
V
°C
mA
mA
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
SOIC/ SSOP/ TSSOP
TOP VIEW
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter(1)
Conditions Typ. Max. Unit
CIN
Input Capacitance
VIN = 0V
4.5
6 pF
COUT
Output Capacitance VOUT = 0V
5.5
8
pF
CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF
NOTE:
1. As applicable to the device type.
PIN DESCRIPTION
Pin Names
xOE
xA
xY
Description
Output-Enable Inputs (Active LOW)
Data Inputs
3-State Outputs
FUNCTION TABLE (EACH BUFFER)(1)
Inputs
Outputs
xOE xA xY
L HH
L LL
H XZ
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-Impedance
2


Part Number IDT74LVC125A
Description 3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O
Maker Integrated Device
Total Page 6 Pages
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