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Integrated Device Technology Electronic Components Datasheet

IDT74FCT2543T Datasheet

FAST CMOS OCTAL LATCHED TRANSCEIVER

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Integrated Device Technology, Inc.
FAST CMOS
OCTAL LATCHED
TRANSCEIVER
IDT54/74FCT543T/AT/CT/DT
IDT54/74FCT2543T/AT/CT
FEATURES:
• Common features:
– Low input and output leakage 1µA (max.)
– CMOS power levels
– True TTL input and output compatibility
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
– Meets or exceeds JEDEC standard 18 specifications
– Product available in Radiation Tolerant and Radiation
Enhanced versions
– Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
– Available in DIP, SOIC, SSOP, QSOP, CERPACK
and LCC packages
• Features for FCT543T:
– Std., A, C and D speed grades
– High drive outputs (-15mA IOH, 64mA IOL)
– Power off disable outputs permit “live insertion”
• Features for FCT2543T:
– Std., A, and C speed grades
– Resistor outputs (-15mA IOH, 12mA IOL Com.)
(-12mA IOH, 12mA IOL Mil.)
– Reduced system switching noise
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The FCT543T/FCT2543T is a non-inverting octal trans-
ceiver built using an advanced dual metal CMOS technology.
This device contains two sets of eight D-type latches with
separate input and output controls for each set. For data flow
from A to B, for example, the A-to-B Enable (CEAB) input must
be LOW in order to enter data from A0–A7 or to take data from
B0–B7, as indicated in the Function Table. With CEAB LOW,
a LOW signal on the A-to-B Latch Enable (LEAB) input makes
the A-to-B latches transparent; a subsequent LOW-to-HIGH
transition of the LEAB signal puts the A latches in the storage
mode and their outputs no longer change with the A inputs.
With CEAB and OEAB both LOW, the 3-state B output buffers
are active and reflect the data present at the output of the A
latches. Control of data from B to A is similar, but uses the
CEBA, LEBA and OEBA inputs.
The FCT2543T has balanced output drive with current
limiting resistors. This offers low ground bounce, minimal
undershoot and controlled output fall times-reducing the need
for external series terminating resistors. FCT2xxxT parts are
plug-in replacements for FCTxxxT parts.
DQ
DETAIL A
B0
LE
A0 Q D
LE
A1
A2
A3
A4 DETAIL A x 7
A5
A6
A7
OEBA
CEBA
LEBA
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995 Integrated Device Technology, Inc.
6.17
B1
B2
B3
B4
B5
B6
B7
OEAB
CEAB
LEAB
2613 drw 01
JANUARY 1995
DSC-4203/5
1


Integrated Device Technology Electronic Components Datasheet

IDT74FCT2543T Datasheet

FAST CMOS OCTAL LATCHED TRANSCEIVER

No Preview Available !

IDT54/74FCT543T/AT/CT/DT - 2543T/AT/CT
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
LEBA
OEBA
A0
A1
A2
A3
A4
A5
A6
A7
CEAB
GND
1 24
2 23
3 22
4 P24-1 21
5 D24-1 20
SO24-2
6 SO24-7 19
7 SO24-8 18
8 & 17
9 E24-1 16
10 15
11 14
12 13
Vcc
CEBA
B0
B1
B2
B3
B4
B5
B6
B7
LEAB
OEAB
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
2613 drw 02
INDEX
4 3 2 28 27 26
A1 5
A2 6
1 25 B1
24 B2
A3 7
23 B3
NC 8
A4 9
L28-1
22 NC
21 B4
A5 10
20 B5
A6 11
19 B6
12 13 14 15 16 17 18
LCC
TOP VIEW
2613 drw 03
PIN DESCRIPTION
Pin Names
OEAB
OEBA
CEAB
CEBA
LEAB
LEBA
Description
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A0–A7
A-to-B Data Inputs or B-to-A 3-State Outputs
B0–B7
B-to-A Data Inputs or A-to-B 3-State Outputs
ABSOLUTE MAXIMUM RATINGS(1)
2613 tbl 01
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND
TA Operating
Temperature
TBIAS Temperature
Under Bias
TSTG Storage
Temperature
PT Power Dissipation
Commercial
–0.5 to +7.0
–0.5 to
VCC +0.5
0 to +70
–55 to +125
–55 to +125
0.5
Military
–0.5 to +7.0
–0.5 to
VCC +0.5
–55 to +125
–65 to +135
–65 to +150
0.5
Unit
V
V
°C
°C
°C
W
IOUT
DC Output
–60 to +120 –60 to +120 mA
Current
NOTES:
2613 lnk 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
FUNCTION TABLE(1, 2)
For A-to-B (Symmetric with B-to-A)
Inputs
CEAB LEAB OEAB
Latch
Status
A-to-B
Output
Buffers
B0–B7
H — — Storing
High Z
— H — Storing
—— H
— High Z
L L L Transparent Current A Inputs
L H L Storing
Previous* A Inputs
NOTES:
1. * Before LEAB LOW-to-HIGH Transition
2613 tbl 02
H = HIGH Voltage Level
L = LOW Voltage Level
— = Don’t Care or Irrelevant
2. A-to-B data flow shown; B-to-A flow control is the same, except using
CEBA, LEBA and OEBA.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN Input
VIN = 0V 6 10 pF
Capacitance
COUT Output
VOUT = 0V 8
12 pF
Capacitance
NOTE:
2613 lnk 04
1. This parameter is measured at characterization but not tested.
6.17 2


Part Number IDT74FCT2543T
Description FAST CMOS OCTAL LATCHED TRANSCEIVER
Maker Integrated Device Tech
Total Page 7 Pages
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