79RC32435 - Communications Processor

Features

x 32-bit CPU Core.
MIPS32 instruction set.
Cache Sizes: 8KB instruction and data caches, 4-Way set associative, cache line locking, non-blocking prefetches.
16 dual-entry JTLB with variable page sizes.
3-entry instruction TLB.
3-entry data TLB.
Max issue rate of one 32x16 multiply per clock.
Max issue rate of one 32x32 multiply every other clock.
CPU control with start, stop, and single stepping.
Software breakpoint.

Integrated Device Technology

Datasheet Details

Part number	79RC32435
Manufacturer	Integrated Device Technology
File Size	0.99 MB
Description	Communications Processor
Datasheet	79RC32435 Datasheet
Additional preview pages of the 79RC32435 datasheet.

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Full PDF Text Transcription

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IDTTM InterpriseTM Integrated Communications Processor 79RC32435 Device Overview The 79RC32435 is a member of the IDT™ Interprise™ family of PCI integrated communications processors. It incorporates a high performance CPU core and a number of on-chip peripherals. The integrated processor is designed to transfer information from I/O modules to main memory with minimal CPU intervention, using a highly sophisticated direct memory access (DMA) engine. All data transfers through the RC32435 are achieved by writing data from an on-chip I/O peripheral to main memory and then out to another I/O module.

Published: Sep 19, 2008 |