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ICS854S054I - 4:1 Differential-to-LVDS Clock Multiplexer

Description

The ICS854S054I is a 4:1 Differential-to-LVDS Clock Multiplexer which can operate up to 2.5GHz.

The ICS854S054I has 4 selectable differential clock inputs.

The PCLK, nPCLK input pairs can accept LVPECL, LVDS or CML levels.

Features

  • High speed 4:1 differential multiplexer.
  • One differential LVDS output pair.
  • Four selectable differential PCLK, nPCLK input pairs.
  • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML.
  • Maximum output frequency: 2.5GHz.
  • Translates any single ended input signal to LVDS levels with resistor bias on nPCLKx input.
  • Additive phase jitter, RMS: 0.147ps (typical).
  • Part-to-part skew: 300ps (maximum.

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Datasheet Details

Part number ICS854S054I
Manufacturer Integrated Device Technology
File Size 1.15 MB
Description 4:1 Differential-to-LVDS Clock Multiplexer
Datasheet download datasheet ICS854S054I Datasheet
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Full PDF Text Transcription

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4:1 Differential-to-LVDS Clock Multiplexer ICS854S054I DATA SHEET General Description The ICS854S054I is a 4:1 Differential-to-LVDS Clock Multiplexer which can operate up to 2.5GHz. The ICS854S054I has 4 selectable differential clock inputs. The PCLK, nPCLK input pairs can accept LVPECL, LVDS or CML levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. The select pins have internal pulldown resistors. The SEL1 pin is the most significant bit and the binary number applied to the select pins will select the same numbered data input (i.e., 00 selects PCLK0, nPCLK0).
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