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ICS854S054I Datasheet, Integrated Device Technology

ICS854S054I multiplexer equivalent, 4:1 differential-to-lvds clock multiplexer.

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ICS854S054I Datasheet

Features and benefits


* High speed 4:1 differential multiplexer
* One differential LVDS output pair
* Four selectable differential PCLK, nPCLK input pairs
* PCLKx, nPCLKx pairs.

Application

Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental.

Description

The ICS854S054I is a 4:1 Differential-to-LVDS Clock Multiplexer which can operate up to 2.5GHz. The ICS854S054I has 4 selectable differential clock inputs. The PCLK, nPCLK input pairs can accept LVPECL, LVDS or CML levels. The fully differential arch.

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TAGS

ICS854S054I
Differential-to-LVDS
Clock
Multiplexer
ICS854S057BI
ICS854S058I
ICS854S006I
Integrated Device Technology

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