ICS874003-04 Datasheet | Integrated Device Technology

Description The ICS874003-04 is a high performance Differential-to-LVDS Jitter Attenuator designed for use Hi Per Clock S™ in PCI Express systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express TM clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter ponents from the PLL synthesizer and from the system board. The ICS874003-04 has a bandwidth of 6.8MHz. The 6.8MHz provides a high bandwidth that can easily track triangular spread profiles, while providing jitter attenuation. Features - - - - - - - - - - - Three differential LVDS output pairs One differential clock input CLK/n CLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL Input frequency range: 98MHz to 128MHz Output frequency range: 98MHz to 320MHz VCO range: 490MHz - 640MHz Supports PCI-Express Spread-Spectrum Clocking High PLL bandwidth allows for better input tracking Full 3.3V supply mode 0°C to 70°C ambient operating temperature Available in both standard (Ro HS 5) and lead-free (Ro HS 6) packages The ICS874003-04 uses IDT’s 3rd Generation Femto Clock™ PLL technology to achieve the lowest possible phase noise. The device is packaged in a 20 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards. Pin Assignment F_SEL[2:0] Function Table Inputs F_SEL2 0 1 0 1 0 1 0 1 F_SEL1 0 0 1 1 0 0 1 1 F_SEL0 0 0 0 0 1 1 1 1 Outputs QA[0:1], n QA[0:1] ÷2 ÷5 ÷4 ÷2 ÷2 ÷5 ÷4 ÷4 QB, n QB0 ÷2 ÷2 ÷2 ÷4 ÷5 ÷4 ÷5 ÷4 QA1 VDDO QA0 n QA0 MR F_SEL0 nc VDDA F_SEL1 VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 n QA1 VDDO QB0 n QB0 F_SEL2 OEB GND n CLK CLK OEA 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View ICS874003AG-04 REVISION A NOVEMBER 4, 2009 ©2009 Integrated Device Technology, Inc. ICS874003-04 Data Sheet PCI...