ICS87974I Datasheet PDF - Integrated Device Technology LVCMOS/LVTTL CLOCK GENERATOR Specs

ICS87974I - LVCMOS/LVTTL CLOCK GENERATOR

Datasheet Summary

Description

The ICS87974I is a low skew, low jitter 1-to-15 LVCMOS/ LVTTL Clock Generator/Zero Delay Buffer.

The device has a fully integrated PLL and three banks whose divider ratios can be independently controlled, providing output frequency relationships of 1:1, 2:1, 3:1, 3:2, 3:2:1.

Features

Fully integrated PLL.
Fifteen single ended 3.3V LVCMOS/LVTTL outputs.
Two LVCMOS/LVTTL clock inputs for redundant clock.

Datasheet Details

Part number	ICS87974I
Manufacturer	Integrated Device Technology
File Size	157.47 KB
Description	LVCMOS/LVTTL CLOCK GENERATOR
Datasheet	ICS87974I Datasheet
Additional preview pages of the ICS87974I datasheet.

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Full PDF Text Transcription

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ICS87974I LOW SKEW, 1-TO-15, LVCMOS/LVTTL CLOCK GENERATOR GENERAL DESCRIPTION The ICS87974I is a low skew, low jitter 1-to-15 LVCMOS/ LVTTL Clock Generator/Zero Delay Buffer. The device has a fully integrated PLL and three banks whose divider ratios can be independently controlled, providing output frequency relationships of 1:1, 2:1, 3:1, 3:2, 3:2:1. In addition, the external feedback connection provides for a wide selection of output-to-input frequency ratios. The CLK0 and CLK1 pins allow for redundant clocking on the input and dynamically switching the PLL between two clock sources. Guaranteed low jitter and output skew characteristics make the ICS87974I ideal for those applications demanding well defined performance and repeatability.

Published: Jan 27, 2016 |