ICS9LP525-2 Datasheet PDF (56-pin CK505 Clock) | Download Integrated Device Technology ICS9LP525-2

ICS9LP525-2 - 56-pin CK505 Clock

Description

3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus.

Features

2 - CPU differential low power push-pull pairs.
7- SRC differential low power push-pull pairs.
1 - CPU/SRC selectable differential low power push-pull pair.
1 - SRC/DOT selectable differential low power push-pull pair.
5 - PCI, 33MHz.
1 - PCI_F, 33MHz free running.
1 - USB, 48MHz.
1 - REF, 14.318MHz Key Specifications:.
CPU outputs cycle-cycle jitter < 85ps.
SRC output cycle-cycle jitter < 125ps.

Datasheet Details

Part number	ICS9LP525-2
Manufacturer	Integrated Device Technology
File Size	269.62 KB
Description	56-pin CK505 Clock
Datasheet	ICS9LP525-2 Datasheet
Additional preview pages of the ICS9LP525-2 datasheet.

📁 Similar Datasheet

ICS9LP525-2 - 56-pin CK505 Clock (Renesas)

ICS9LPR426A - Low Power Programmable Timing Control Hub (Integrated Circuit Systems)

ICS9LPR501 - 64-pin CK505 w/Fully Integrated Voltage Regulator (ICS)

ICS9LPRS365 - 64-Pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor (ICS)

ICS9LPRS501 - 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR (Renesas)

ICS9LPRS501 - 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR (IDT)

ICS9LPRS502 - 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR (IDT)

ICS9LPRS525 - 56-pin CK505 (Renesas)

ICS9LPRS535 - VREG (Renesas)

ICS9LPRS545 - 48-pin CK505 (Integrated Circuit Solution)

Full PDF Text Transcription

Click to expand full text

www.DataSheet4U.net DATASHEET 56-pin CK505 for Intel Desktop Systems Recommended Application: CK505 clock, 56-pin Intel Yellow Cover part Output Features: • 2 - CPU differential low power push-pull pairs • 7- SRC differential low power push-pull pairs • 1 - CPU/SRC selectable differential low power push-pull pair • 1 - SRC/DOT selectable differential low power push-pull pair • 5 - PCI, 33MHz • 1 - PCI_F, 33MHz free running • 1 - USB, 48MHz • 1 - REF, 14.318MHz Key Specifications: • CPU outputs cycle-cycle jitter < 85ps • SRC output cycle-cycle jitter < 125ps • PCI outputs cycle-cycle jitter < 250ps • +/- 100ppm frequency accuracy on all outputs • SRC are PCIe Gen2 compliant ICS9LP525-2 Features/Benefits: • Supports spread spectrum modulation, default is 0.

Published: Sep 5, 2011 |