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ICS9LPRS525 - 56-pin CK505

Description

3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus.

Features

  • 2 - CPU differential low power push-pull pairs.
  • 7 - SRC differential push-pull pairs.
  • 1 - CPU/SRC selectable differential low power push-pull pair.
  • 1 - SRC/DOT selectable differential low power push-pull pair.
  • 1 - SRC/SE selectable differential push-pull pair/Single-ended outputs.
  • 5 - PCI, 33MHz.
  • 1 - USB, 48MHz.
  • 1 - REF, 14.318MHz Key Specifications:.
  • CPU outputs cycle-cycle jitter < 85ps.
  • SRC output cycl.

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Datasheet preview – ICS9LPRS525

Datasheet Details

Part number ICS9LPRS525
Manufacturer Integrated Device Technology
File Size 271.98 KB
Description 56-pin CK505
Datasheet download datasheet ICS9LPRS525 Datasheet
Additional preview pages of the ICS9LPRS525 datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com DATASHEET 56-pin CK505 for Intel Systems Recommended Application: 56-pin CK505 compatible clock, w/fully integrated Vreg and series resistors on differential outputs Output Features: • 2 - CPU differential low power push-pull pairs • 7 - SRC differential push-pull pairs • 1 - CPU/SRC selectable differential low power push-pull pair • 1 - SRC/DOT selectable differential low power push-pull pair • 1 - SRC/SE selectable differential push-pull pair/Single-ended outputs • 5 - PCI, 33MHz • 1 - USB, 48MHz • 1 - REF, 14.
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