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Integrated Device Technology Electronic Components Datasheet

IDT72021 Datasheet

(IDT720x1) CMOS ASYNCHRONOUS FIFO

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Integrated Device Technology, Inc.
CMOS ASYNCHRONOUS FIFO WITH
RETRANSMIT
1K x 9, 2K x 9, 4K x 9
IDT72021
IDT72031
IDT72041
FEATURES:
• First-In/First-Out Dual-Port memory
• Bit organization
– IDT72021—1K x 9
– IDT72031—2K x 9
– IDT72041—4K x 9
• Ultra high speed
– IDT72021—25ns access time
– IDT72031—35ns access time
www.DataSheet4UID.cTom72041—35ns access time
• Easily expandable in word depth and/or width
• Asynchronous and simultaneous read and write
• Functionally equivalent to IDT7202/03/04 with Output
Enable (OE ) and Almost Empty/Almost Full Flag (AEF )
• Four status flags: Full, Empty, Half-Full (single device
mode), and Almost Empty/Almost Full (7/8 empty or 7/8
full in single device mode)
• Output Enable controls the data output port
• Auto-retransmit capability
• Available in 32-pin DIP and PLCC
• Military product compliant to MIL-STD-883, Class B
• Industrial temperature range (-40oC to +85oC) is avail
able, tested to military electrical specifications
DESCRIPTION:
IDT72021/031/041s are high-speed, low-power, dual-port
memory devices commonly known as FIFOs (First-In/First-
Out). Data can be written into and read from the memory at
independent rates. The order of information stored and ex-
tracted does not change, but the rate of data entering the FIFO
might be different than the rate leaving the FIFO. Unlike a
Static RAM, no address information is required because the
read and write pointers advance sequentially. The IDT72021/
031/041s can perform asynchronous and simultaneous read
and write operations. There are four status flags, (HF , FF , EF ,
AEF ) to monitor data overflow and underflow. Output Enable
(OE ) is provided to control the flow of data through the output
port. Additional key features are Write (W ), Read (R ), Retrans-
mit (RT ), First Load (FL ), Expansion In (XI ) and Expansion Out
(XO ). The IDT72021/031/041s are designed for those appli-
cations requiring data control flags and Output Enable (OE ) in
multiprocessing and rate buffer applications.
The IDT72021/031/041s are fabricated using IDT’s CMOS
technology. Military grade product is manufactured in compli-
ance with the latest version of MIL-STD-883, Class B, for high
reliability systems.
FUNCTIONAL BLOCK DIAGRAM
DATA INPUT
(D0–D8)
W
WRITE
CONTROL
WRITE
POINTER
1
2
RAM
ARRAY
1024 x 9
2048 x 9
4096 x 9
1024/
2048/
4096
READ
POINTER
OE
THREE-
STATE
BUFFERS
RESET
LOGIC
RS
FL/RT
R
READ
CONTROL
DATA OUTPUTS
(Q0–Q8)
FLAG
LOGIC
EXPANSION
XI LOGIC
EF
FF
AEF
XO/HF
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
2677 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.09
DECEMBER 1996
DSC-2677/7
1


Integrated Device Technology Electronic Components Datasheet

IDT72021 Datasheet

(IDT720x1) CMOS ASYNCHRONOUS FIFO

No Preview Available !

IDT72021, IDT72031, IDT72041
CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
D2
D1
D0
XI
AEF
FF
Q0
Q1
www.DataSheet4U.com
Q2
4 3 2 1 32 31 30
5 29
6 28
7 27
8
J32-1
26
9 25
10 24
11 23
12 22
13 21
14 15 16 17 18 19 20
D6
D7
FL /RT
RS
OE
EF
XO /HF
Q7
Q6
PLCC TOP VIEW
2677 drw 03
VCC
W
D8
D3
D2
D1
D0
XI
AEF
FF
Q0
Q1
Q2
Q3
Q8
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D32-1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
DIP TOP VIEW
VCC
D4
D5
D6
D7
FL /RT
RS
OE
EF
XO /HF
Q7
Q6
Q5
Q4
R
GND
2677 drw 02
PIN DESCRIPTIONS
Symbol Name
D0–D8
Inputs
RS Reset
I/O
I
I
W Write
I
R Read
I
FL /RT
XI
OE
First Load/
Retransmit
I
Expansion In
Output Enable
I
I
FF
EF
AEF
XO /HF
Full Flag
O
Empty Flag
O
Almost-Empty/
Almost-Full Flag
Expansion Out/
Half-Full Flag
O
O
Q0–Q8
Outputs
O
Description
Data inputs for 9-bit wide data.
When RS is set LOW, internal READ and WRITE pointers are set to the first location of the RAM
array. HF and FF go HIGH, and AEF and EF go LOW. A reset is required before an initial WRITE
after power-up. R and W must be HIGH during RS cycle.
When WRITE is LOW, data can be written into the RAM array sequentially, independent of
READ. In order for WRITE to be active, FF must be HIGH. When the FIFO is full (FF -LOW),
the internal WRITE operation is blocked.
When READ is LOW, data can be read from the RAM array sequentially, independent of
WRITE. In order for READ to be active, EF must be HIGH. When the FIFO is empty (EF -LOW),
the internal READ operation is blocked. The three-state output buffer is controlled by the read
signal and the external output control (OE ).
This is a dual-purpose input. In the single device configuration (XI grounded), activating
retransmit (FL /RT -LOW) will set the internal READ pointer to the first location. There is no effect
on the WRITE pointer. R and W must be HIGH before setting FL /RT LOW. Retransmit is not
compatible with depth expansion. In the depth expansion configuration, FL /RT -LOW indicates
the first activated device.
In the single device configuration, XI is grounded. In depth expansion or daisy chain expansion,
XI is connected to XO (expansion out) of the previous device.
When OE is set HIGH, the data flow through the three-state output buffer is inhibited regardless
of an active READ operation. A read operation does increment the read pointer in this situation.
When OE is set LOW, Q0-Q8 are still in a HIGH impedance condition if no READ occurs. For
a complete READ operation with data appearing on Q0-Q8, both R and OE should be asserted
LOW.
When FF goes LOW, the device is full and further WRITE operations are inhibited. When FF
is HIGH, the device is not full.
When EF goes LOW, the device is empty and further READ operations are inhibited. When EF
is HIGH, the device is not empty.
When AEF is LOW, the device is empty to 1/8 full or 7/8 to completely full. When AEF is HIGH,
the device is greater than 1/8 full, but less than 7/8 full.
This is a dual purpose output. In the single device configuration (XI grounded), the device is
more than half full when HF is LOW. In the depth expansion configuration (XO connected to
XI of the next device), a pulse is sent from XO to XI when the last location in the RAM array is
filled.
Data outputs for 9-bit wide data.
2677 tbl 01
5.09 2


Part Number IDT72021
Description (IDT720x1) CMOS ASYNCHRONOUS FIFO
Maker Integrated Device Technology
PDF Download

IDT72021 Datasheet PDF






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