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Integrated Device Technology Electronic Components Datasheet

IDT72420 Datasheet

FIFO memories

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CMOS SyncFIFO™
64 x 8, 256 x 8,
512 x 8, 1,024 x 8,
2,048 x 8 and 4,096 x 8
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
IDT72420
IDT72200
IDT72210
IDT72220
IDT72230
IDT72240
FEATURES:
64 x 8-bit organization (IDT72420)
256 x 8-bit organization (IDT72200)
512 x 8-bit organization (IDT72210)
1,024 x 8-bit organization (IDT72220)
2,048 x 8-bit organization (IDT72230)
4,096 x 8-bit organization (IDT72240)
10 ns read/write cycle time (IDT72420/72200/72210/72220/72230/
72240)
Read and Write Clocks can be asynchronous or coincidental
Dual-Ported zero fall-through time architecture
Empty and Full flags signal FIFO status
Almost-Empty and Almost-Full flags set to Empty+7 and Full-7,
respectively
Output enable puts output data bus in high-impedance state
Produced with advanced submicron CMOS technology
Available in 28-pin 300 mil plastic DIP
For surface mount product please see the IDT72421/72201/72211/
72221/72231/72241 data sheet
Green parts available, see ordering information
DESCRIPTION:
The IDT72420/72200/72210/72220/72230/72240 SyncFIFO™ are very
high-speed,low-powerFirst-In,First-Out(FIFO)memorieswithclocked read
and write controls. These devices have a 64, 256, 512, 1,024, 2,048, and 4,096
x 8-bit memory array, respectively. These FIFOs are applicable for a wide
variety of data buffering needs, such as graphics, Local Area Networks (LANs),
and interprocessor communication.
These FIFOs have 8-bit input and output ports. The input port is controlled
byafree-runningclock(WCLK),andaWriteEnablepin(WEN). Dataiswritten
into the Synchronous FIFO on every clock when WEN is asserted. The output
port is controlled by another clock pin (RCLK) and a Read Enable pin (REN).
The Read Clock can be tied to the Write Clock for single clock operation or the
two clocks can run asynchronous of one another for dual clock operation. An
Output Enable pin (OE) is provided on the read port for three-state control of
the output.
These Synchronous FIFOs have two endpoint flags, Empty (EF) and Full
(FF). Two partial flags, Almost-Empty (AE) and Almost-Full (AF), are provided
for improved system control. The partial (AE) flags are set to Empty+7 and Full-
7 for AE and AF respectively.
These FIFOs are fabricated using high-speed submicron CMOS technol-
ogy.
FUNCTIONAL BLOCK DIAGRAM
WCLK
WEN
D0 - D7
WRITE CONTROL
LOGIC
WRITE POINTER
INPUT REGISTER
RAM ARRAY
64 x 8, 256 x 8,
512 x 8, 1,024 x 8,
2,048 x 8, 4,096 x 8
FLAG
LOGIC
READ POINTER
READ CONTROL
LOGIC
EF
AE
AF
FF
OUTPUT REGISTER
RESET LOGIC
RS OE
Q0 - Q7
RCLK
REN
2680 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
©2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
FEBRUARY 2018
DSC-2680/7


Integrated Device Technology Electronic Components Datasheet

IDT72420 Datasheet

FIFO memories

No Preview Available !

IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™
64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
PIN CONFIGURATION
COMMERCIALTEMPERATURERANGE
D4 1
28 D5
D3 2
27 D6
D2 3
D1 4
D0 5
AF 6
AE 7
26 D7
25 RS
24 WEN
23 WCLK
22 VCC
GND 8
21 Q7
RCLK
REN
OE
EF
FF
Q0
9
10
11
12
13
14
20 Q6
19 Q5
18 Q4
17 Q3
16 Q2
15 Q1
2680 drw02
PLASTIC THIN DIP (P28-2, order code: TP)
TOP VIEW
PIN DESCRIPTIONS
Symbol
Name
I/O
Description
D0 - D7
Data Inputs
I Data inputs for a 8-bit bus.
RS Reset
I When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF and AF go
HIGH, and AE and EF go LOW. A reset is required before an initial WRITE after power-up.
WCLK
Write Clock
I Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when WEN is asserted.
WEN Write Enable
I When WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK. Data will not be written
into the FIFO if the FF is LOW.
Q0 - Q7 Data Outputs
O Data outputs for a 8-bit bus.
RCLK
Read Clock
I Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN is asserted.
REN Read Enable I When REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data will not be read from
the FIFO if the EF is LOW.
OE
Output Enable
I When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance
state.
EF Empty Flag O When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is HIGH, the FIFO
is not empty. EF is synchronized to RCLK.
AE Almost-Empty Flag O When AE is LOW, the FIFO is almost empty based on the offset Empty+7. AE is synchronized to RCLK.
AF Almost-Full Flag O When AF is LOW, the FIFO is almost full based on the offset Full-7. AF is synchronized to WCLK.
FF Full Flag
O When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO is not
full. FF is synchronized to WCLK.
VCC Power
One +5 volt power supply pin.
GND Ground
One 0 volt ground pin.
2


Part Number IDT72420
Description FIFO memories
Maker Integrated Device Technology
Total Page 11 Pages
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