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IDT72T36105 Datasheet

2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS

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2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS
65,536 x 36
131,072 x 36
262,144 x 36
IDT72T36105
IDT72T36115
IDT72T36125
FEATURES:
Choose among the following memory organizations:
IDT72T36105 65,536 x 36
IDT72T36115 131,072 x 36
IDT72T36125 262,144 x 36
Up to 225 MHz Operation of Clocks
User selectable HSTL/LVTTL Input and/or Output
2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
3.3V Input tolerant
Read Enable & Read Clock Echo outputs aid high speed operation
User selectable Asynchronous read and/or write port timing
Mark & Retransmit, resets read pointer to user marked position
Write Chip Select (WCS) input enables/disables Write operations
Read Chip Select (RCS) synchronous to RCLK
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Program programmable flags by either serial or parallel means
Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
Separate SCLK input for Serial programming of flag offsets
User selectable input and output port bus-sizing
- x36 in to x36 out
- x36 in to x18 out
- x36 in to x9 out
- x18 in to x36 out
- x9 in to x36 out
Big-Endian/Little-Endian user selectable byte representation
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty, Full and Half-Full flags signal FIFO status
Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
Output enable puts data outputs into high impedance state
JTAG port, provided for Boundary Scan function
Available in 240-pin (19mm x 19mm) Plastic Ball Grid Array (PBGA)
Easily expandable in depth and width
Independent Read and Write Clocks (permit reading and writing
simultaneously)
High-performance submicron CMOS technology
Industrial temperature range (–40°C to +85°C) is available
Green parts are available, see ordering information
FUNCTIONAL BLOCK DIAGRAM
WEN WCL K/WR
WCS
D0 - Dn (x36, x18 or x9)
LD SEN SCL K
INP UT REGISTER
OF F SET REGISTER
ASYW
BE
IP
WRITE CONTROL
L OGIC
WRITE P OINTER
CONTROL
L OGIC
RAM ARRAY
65,536 x 36
131,072 x36
262,144 x 36
F LAG
L OGIC
READ P OINTER
BM
IW
OW
MRS
PRS
BUS
CONF IGURATION
RESET
L OGIC
OUTP UT REGISTER
READ
CONTROL
L OGIC
TCK
TRST
TMS
TDO
TDI
Vr ef
WHSTL
RHSTL
SHSTL
J TAGCONTROL
(BOUNDARY SCAN)
HSTL I/0
CONTROL
OE
Q0 - Qn (x36, x18 or x9)
EREN
ERCL K
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
© 2017 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
FF/IR
PAF
EF/OR
PAE
HF
F WF T/SI
PF M
F SEL 0
F SEL 1
RT
MARK
ASYR
RCL K/RD
REN
RCS
5907 dr w01
JUNE 2017
DSC-5907/21


Integrated Device Technology Electronic Components Datasheet

IDT72T36105 Datasheet

2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS

No Preview Available !

IDT72T36105/115/125 2.5V TeraSync36-BIT FIFO
64K x 36, 128K x 36 and 256K x 36
PIN CONFIGURATION
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
A1 BALL PAD CORNER
A
VCC
VCC
VCC
VCC
VCC
VCC WCLK PRS GND
FF EREN RCLK OE VDDQ VDDQ VDDQ VDDQ VDDQ
B
VCC VCC VCC VCC VCC VCC WEN MRS GND PAF EF REN RCS VDDQ VDDQ VDDQ VDDQ VDDQ
C
VCC
VCC
VCC
VCC
VCC
VCC WCS
LD
GND
HF
PAE MARK RT VDDQ VDDQ VDDQ VDDQ VDDQ
D
VCC VCC VCC FWFT/SI OW FS0 SHSTL FS1 GND BE IP BM RHSTL ASYR PFM VDDQ VDDQ VDDQ
E
VCC VCC VCC GND
GND VDDQ VDDQ VDDQ
F
VCC VCC VCC GND
GND VDDQ VDDQ VDDQ
G
VCC SEN SCLK WHSTL
GND VDDQ VDDQ VDDQ
H
VCC VCC VCC ASYW
J
VCC VCC VCC VREF
K
VCC VCC VCC
IW
L
D33 D34 D35 GND
M
D30 D31 D32 GND
GND GND GND GND
GND GND GND GND
GND GND GND GND
GND GND GND GND
GND VDDQ VDDQ VDDQ
GND VDDQ VDDQ VDDQ
GND VDDQ VDDQ VDDQ
GND VDDQ Q35 Q34
GND Q33 Q32 Q31
N
D27 D28 D29 GND
P
D24 D25 D26 GND
GND Q30 Q29 Q28
GND Q27 Q26 Q25
R
D21 D22 D23 GND GND GND GND GND GND GND GND GND GND GND GND Q24 Q23 Q22
T
D19 D20 D13 D10
D5
D4
D1 TMS TDO GND Q0
Q2 Q3
Q8 Q11 Q14 Q21 Q20
U
D18 D17 D14 D11 D7
D8 D2 TRST TDI GND Q1 Q6 Q5 Q9 Q12 Q15 Q18 Q19
V
VCC D16 D15 D12
D9
D6
D3 D0 TCK GND ERCLK Q4 Q7 Q10 Q13 Q16 Q17 VDDQ
12
34
56
78
9 10 11 12 13 14 15 16 17 18
5907 drw02A
PBGA: 1mm pitch, 19mm x 19mm BB240, BBG240 (Order code: BB, BBG)
TOP VIEW
2


Part Number IDT72T36105
Description 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS
Maker Integrated Device Technology
Total Page 30 Pages
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