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Integrated Device Technology Electronic Components Datasheet

IDT72T3685 Datasheet

(IDT72T36xxx) 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS

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2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS
1,024 x 36, 2,048 x 36, 4,096 x 36,
8,192 x 36, 16,384 x 36, 32,768 x 36,
65,536 x 36, 131,072 x 36 and 262,144 x 36
IDT72T3645, IDT72T3655, IDT72T3665,
IDT72T3675, IDT72T3685, IDT72T3695,
IDT72T36105, IDT72T36115, IDT72T36125
FEATURES:
Choose among the following memory organizations:
IDT72T3645 1,024 x 36
IDT72T3655 2,048 x 36
IDT72T3665 4,096 x 36
IDT72T3675 8,192 x 36
IDT72T3685 16,384 x 36
IDT72T3695 32,768 x 36
IDT72T36105 65,536 x 36
IDT72T36115 131,072 x 36
IDT72T36125 262,144 x 36
Up to 225 MHz Operation of Clocks
User selectable HSTL/LVTTL Input and/or Output
2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
3.3V Input tolerant
Read Enable & Read Clock Echo outputs aid high speed operation
User selectable Asynchronous read and/or write port timing
Mark & Retransmit, resets read pointer to user marked position
Write Chip Select (WCS) input enables/disables Write operations
Read Chip Select (RCS) synchronous to RCLK
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Program programmable flags by either serial or parallel means
Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
Separate SCLK input for Serial programming of flag offsets
User selectable input and output port bus-sizing
- x36 in to x36 out
- x36 in to x18 out
- x36 in to x9 out
- x18 in to x36 out
- x9 in to x36 out
Big-Endian/Little-Endian user selectable byte representation
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty, Full and Half-Full flags signal FIFO status
Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
Output enable puts data outputs into high impedance state
JTAG port, provided for Boundary Scan function
Available in 208-pin (17mm x 17mm) or 240-pin (19mm x 19mm)
Plastic Ball Grid Array (PBGA)
Easily expandable in depth and width
Independent Read and Write Clocks (permit reading and writing
simultaneously)
High-performance submicron CMOS technology
Industrial temperature range (–40°C to +85°C) is available
FUNCTIONAL BLOCK DIAGRAM
WEN WCLK/WR
D0 -Dn (x36, x18 or x9)
LD SEN SCLK
WCS
INPUT REGISTER
OFFSET REGISTER
ASYW
BE
IP
WRITE CONTROL
LOGIC
WRITE POINTER
CONTROL
LOGIC
RAM ARRAY
1,024 x 36, 2,048 x 36
4,096 x 36, 8,192 x 36
16,384 x 36, 32,768 x 36
65,536 x 36, 131,072 x36
262,144 x 36
FLAG
LOGIC
READ POINTER
BM
IW
OW
MRS
PRS
BUS
CONFIGURATION
RESET
LOGIC
OUTPUT REGISTER
READ
CONTROL
LOGIC
TCK
TRST
TMS
TDO
TDI
Vref
WHSTL
RHSTL
SHSTL
JTAG CONTROL
(BOUNDARY SCAN)
HSTL I/0
CONTROL
OE
Q0 -Qn (x36, x18 or x9)
EREN
ERCLK
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
RT
MARK
ASYR
RCLK/RD
REN
RCS
5907 drw01
SEPTEMBER 2003
DSC-5907/17


Integrated Device Technology Electronic Components Datasheet

IDT72T3685 Datasheet

(IDT72T36xxx) 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS

No Preview Available !

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
PIN CONFIGURATION
A1 BALL PAD CORNER
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
A
WCS SCLK WEN WCLK MRS FWFT/SI PAF FSO SHSTL IP RHSTL PAE EF REN RCLK RT
B
SEN ASYW WHSTL PRS
LD
FF OW
HF FSI
BE BM ASYR PFM EREN MARK RCS
C
VREF IW
VCC VCC
VCC VCC VCC
VCC VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ Q35
OE
D
D35 D34 VCC VCC VCC GND GND GND GND GND GND VCC VDDQ VDDQ Q33 Q34
E
D33 D32 VCC VCC
VCC VDDQ Q31 Q32
F
D31 D30 VCC GND
GND VCC Q29 Q30
G
D29 D28
VCC GND
GND GND GND GND
GND VCC Q27
Q28
H
D27 D26 VCC GND
J
D24 D25 VCC GND
GND GND GND GND
GND GND GND GND
GND VCC Q25 Q26
GND VCC Q23 Q24
K
D22 D23 VCC GND
GND GND GND GND
GND VCC Q22 Q21
L
D20 D21 VCC GND
GND VCC Q20 Q19
M
D18 D19 VCC VCC
VCC VDDQ Q18
Q17
N
D16 D17
VCC VCC VCC GND GND GND GND GND GND VCC VDDQ VDDQ Q16
Q15
P
D14 D15
VCC
VCC
VCC VCC VCC
VCC VDDQ VDDQ VDDQ VDDQ VDDQ Q14 Q13
Q12
R
D11 D12 D13 D6 D4 D2 D0 TMS TCK TDO Q0 Q2 Q4 Q6 Q11 Q10
T
D9 D10 D8
D7 D5
D3 D1 TRST TDI ERCLK Q1
Q3 Q5
Q7 Q9
Q8
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
5907 drw02
IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695 Only
PBGA: 1mm pitch, 17mm x 17mm (BB208-1, order code: BB)
TOP VIEW
2


Part Number IDT72T3685
Description (IDT72T36xxx) 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS
Maker Integrated Device Technology
Total Page 30 Pages
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