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Integrated Device Technology Electronic Components Datasheet

IDT72V201 Datasheet

FIFO memories

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3.3 VOLT CMOS SyncFIFO™
256 x 9, 512 x 9,
IDT72V201, IDT72V211
1,024 x 9, 2,048 x 9,
IDT72V221, IDT72V231
4,096 x 9 and 8,192 x 9
IDT72V241, IDT72V251
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
FEATURES:
256 x 9-bit organization IDT72V201
512 x 9-bit organization IDT72V211
1,024 x 9-bit organization IDT72V221
2,048 x 9-bit organization IDT72V231
4,096 x 9-bit organization IDT72V241
8,192 x 9-bit organization IDT72V251
10 ns read/write cycle time
5V input tolerant
Read and Write clocks can be independent
Dual-Ported zero fall-through time architecture
Empty and Full Flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags can be set to
any depth
Programmable Almost-Empty and Almost-Full flags default to
Empty+7, and Full-7, respectively
Output Enable puts output data bus in high-impedance state
Advanced submicron CMOS technology
Available in 32-pin plastic leaded chip carrier (PLCC) and 32-pin
plastic Thin Quad FlatPack (TQFP)
Industrial temperature range (–40°C to +85°C) is available
Green parts available, see ordering information
DESCRIPTION:
The IDT72V201/72V211/72V221/72V231/72V241/72V251 SyncFIFOs™
are very high-speed, low-power First-In, First-Out (FIFO) memories with
clocked read and write controls. The architecture, functional operation and pin
assignments are identical to those of the IDT72201/72211/72221/72231/
72241/72251, but operate at a power supply voltage (Vcc) between 3.0V and
3.6V. These devices have a 256, 512, 1,024, 2,048, 4,096 and 8,192 x 9-
bit memory array, respectively. These FIFOs are applicable for a wide variety
ofdatabufferingneedssuchasgraphics,localareanetworksandinterprocessor
communication.
These FIFOs have 9-bit input and output ports. The input port is
controlled by a free-running clock (WCLK), and two Write Enable pins
(WEN1, WEN2). Data is written into the Synchronous FIFO on every
rising clock edge when the Write Enable pins are asserted. The output
port is controlled by another clock pin (RCLK) and two Read Enable pins
(REN1, REN2). The Read Clock can be tied to the Write Clock for single
clock operation or the two clocks can run asynchronous of one another
for dual-clock operation. An Output Enable pin (OE) is provided on the
read port for three-state control of the output.
The Synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF).
Two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF), are
provided for improved system control. The programmable flags default to
Empty+7 and Full-7 for PAE and PAF, respectively. The programmable flag
offsetloadingiscontrolledbyasimplestatemachineandisinitiatedbyasserting
the Load pin (LD).
These FIFOs are fabricated using high-speed submicron CMOS
technology.
FUNCTIONAL BLOCK DIAGRAM
WCLK
WEN1
WEN2
D0 - D8
INPUT REGISTER
LD
OFFSET REGISTER
WRITE CONTROL
LOGIC
WRITE POINTER
RAM ARRAY
256 x 9, 512 x 9,
1,024 x 9, 2,048 x 9,
4,096 x 9, 8,192 x 9
FLAG
LOGIC
READ POINTER
EF
PAE
PAF
FF
READ CONTROL
LOGIC
OUTPUT REGISTER
RESET LOGIC
RS
OE
Q0 - Q8
RCLK
REN1
REN2
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
©2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
4092 drw 01
MARCH 2018
DSC-4092/7


Integrated Device Technology Electronic Components Datasheet

IDT72V201 Datasheet

FIFO memories

No Preview Available !

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
PIN CONFIGURATION
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
INDEX
INDEX
D1
D0
PAF
PAE
GND
REN1
RCLK
REN2
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 21
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
WEN1
WCLK
WEN2/LD
VCC
Q8
Q7
Q6
Q5
4092 drw02
TQFP (PR32-1, order code: PF)
TOP VIEW
D1
D0
PAF
PAE
GND
REN1
RCLK
REN2
OE
4 3 2 32 31 30
5 1 29
6 28
7 27
8 26
9 25
10 24
11 23
12 22
13 21
14 15 16 17 18 19 20
RS
WEN1
WCLK
WEN2/LD
VCC
Q8
Q7
Q6
Q5
PLCC (J32-1, order code: J)
TOP VIEW
4092 drw02a
PIN DESCRIPTIONS
Symbol
Name
I/O
Description
D0-D8
Data Inputs
I Data inputs for a 9-bit bus.
RS Reset
I When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF
and PAF go HIGH, and PAE and EF go LOW. A Reset is required before an initial Write after power-up.
WCLK
Write Clock
I Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write Enable(s) are asserted.
WEN1
Write Enable 1
I If the FIFO is configured to have programmable flags, WEN1 is the only Write Enable pin. When WEN1 is
LOW, data is written into the FIFO on every LOW-to-HIGH transition WCLK. If the FIFO is configured to
have two write enables, WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data
will not be written into the FIFO if the FF is LOW.
WEN2/LD Write Enable 2/
Load
I The FIFO is configured at Reset to have either two write enables or programmable flags. If WEN2/LD
is HIGH at Reset, this pin operates as a second write enable. If WEN2/LD is LOW at Reset, this pin operates
as a control to load and read the programmable flag offsets. If the FIFO is configured to have two write
enables, WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written
into the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW to
write or read the programmable flag offsets.
Q0-Q8
Data Outputs
O Data outputs for a 9-bit bus.
RCLK
Read Clock
I Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN1 and REN2 are asserted.
REN1
Read Enable 1
I When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data
will not be read from the FIFO if the EF is LOW.
REN2
OE
Read Enable 2
Output Enable
I When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.
Data will not be read from the FIFO if the EF is CLOOWM.MERCIALANDINDUSTRIAL
I When OE is LOW, the data output bus is active. If OE isTHEIGMHP,EthReAoTuUtpRutEdRaAtaNbGusEwSill be in a high-impedance
state.
EF
Empty Flag
O When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is
HIGH, the FIFO is not empty. EF is synchronized to RCLK.
PAE Programmable O When PAE is LOW, the FIFO is almost-empty based on the offset programmed into the FIFO. The default
Almost-Empty Flag
offset at reset is Empty+7. PAE is synchronized to RCLK.
PAF Programmable O When PAF is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default
Almost-Full Flag
offset at reset is Full-7. PAF is synchronized to WCLK.
FF Full Flag
O When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO
is not full. FF is synchronized to WCLK.
VCC Power
One 3.3V volt power supply pin.
GND Ground
One 0 volt ground pin.
2


Part Number IDT72V201
Description FIFO memories
Maker Integrated Device Technology
Total Page 14 Pages
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