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Integrated Device Technology Electronic Components Datasheet

IDT74FCT16601CT Datasheet

FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

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Integrated Device Technology, Inc.
FAST CMOS
18-BIT UNIVERSAL BUS
TRANSCEIVER
WITH 3-STATE OUTPUTS
IDT74FCT16601AT/CT/ET
IDT74FCT162601AT/CT/ET
PRODUCT PREVIEW
FEATURES:
bit registered transceivers are built using advanced dual metal
• Common features:
CMOS technology. These high-speed, low-power 18-bit reg-
– 0.5 MICRON CMOS Technology
istered bus transceivers combine D-type latches and D-type
– High-speed, low-power CMOS replacement for
flip-flops to allow data flow in either direction in a transparent,
ABT functions
latched or clocked mode. Each direction has an independent
Typical tSK(o) (Output Skew) < 250ps
latch enable, an independent clock with a clock enable, and an
– Low input and output leakage 1µA (max.)
independent output enable. The package is organized with a
– ESD > 2000V per MIL-STD-883, Method 3015;
flow-through signal pin organization to ease board layout. All
> 200V using machine model (C = 200pF, R = 0)
inputs are designed with hysteresis for improved noise mar-
– Packages include 25 mil pitch SSOP, 19.6 mil pitch
gin.
WTSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack This transceiver is ideally suited for high speed memory
– Extended commercial range of -40°C to +85°C
interfaces which utilize high speed synchronous writes, by
E– VCC = 5V ±10%
clocking the data into a high speed register. Reads can then
I• Features for FCT16601AT/CT/ET:
be performed in a transparent or latched mode utilizing the
– High drive outputs (-32mA IOH, 64mA IOL)
same transceiver.
V– Power off disable outputs permit “live insertion”
The FCT16601AT/CT/ET are ideally suited for driving
– Typical VOLP (Output Ground Bounce) < 1.0V at
VCC = 5V, TA = 25°C
Ehigh-capacitance loads and low-impedance backplanes. The
output buffers are designed with power off disable capability
• Features for FCT162601AT/CT/ET:
– Balanced Output Drivers: ±24mA
– Reduced system switching noise
– Typical VOLP (Output Ground Bounce) < 0.6V at
VCC = 5V,TA = 25°C
Rto allow "live insertion" of boards when used as backplane
drivers.
The FCT162601AT/CT/ET have balanced output drive
Pwith current limiting resistors. This offers low ground bounce,
minimal undershoot, and controlled output fall times–reducing
the need for external series terminating resistors. The
DESCRIPTION:
TFCT162601AT/CT/ET are plug-in replacements for the
FCT16601AT/CT/ET and ABT16601 for on-board bus inter-
The FCT16601AT/CT/ET and FCT162601AT/CT/ET 18- face applications.
CFUNCTIONAL BLOCK DIAGRAM
OEAB 1
CLKENAB 56
CLKAB 55
U
D
2
LEAB
28
LEBA
O
R30
CLKBA
PCLKENBA 29
27
OEBA
3
A1
CE
1D
C1
CLK
CE
1D
C1
CLK
54 B1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
TO 17 OTHER CHANNELS
5.9
3247 drw 01
AUGUST 1996
DSC-3247/-
1


Integrated Device Technology Electronic Components Datasheet

IDT74FCT16601CT Datasheet

FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

No Preview Available !

IDT74FCT16601AT/CT/ET, 162601AT/CT/ET
FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
OEAB
LEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
1 56
2 55
3 54
4 53
5 52
6 51
7 50
8 49
9 48
10 47
11 46
12 45
13 44
14 SO56-1 43
SO56-2
15 SO56-3 42
16 41
17 40
18 39
19 38
20 37
CLKENAB
CLKAB
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
VTERM(2) Terminal Voltage with Respect to
GND
VTERM(3) Terminal Voltage with Respect to
GND
TSTG Storage Temperature
Max.
–0.5 to +7.0
–0.5 to
VCC +0.5
–65 to +150
Unit
V
V
°C
IOUT DC Output Current
–60 to +120 mA
NOTES:
3247 lnk 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
W2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
IECAPACITANCE (TA = +25°C, f = 1.0MHz)
VSymbol Parameter(1)
CIN Input
Conditions Typ.
VIN = 0V
3.5
ECapacitance
CI/O I/O
VOUT = 0V 3.5
Max.
6.0
8.0
Unit
pF
pF
RNOTE:
Capacitance
3247 lnk 04
P1. This parameter is measured at characterization but not tested.
A15 21
VCC 22
A16 23
A17 24
36 B15
35 VCC
34 B16
33 B17
T
C FUNCTION TABLE(1,4)
GND
A18
OEBA
25
26
27
U32 GND
31 B18
D30 CLKBA
CLKENAB OEAB
XH
XL
Inputs
LEAB
X
H
CLKAB
X
X
Outputs
AB
XZ
LL
LEBA
O28 29
SSOP/
CLKENBA
TSSOP/TVSOP
TOP VIEW
RPIN DESCRIPTION
3247 drw 02
Pin Names
OEAB
PDescription
A-to-B Output Enable Input (Active LOW)
OEBA
B-to-A Output Enable Input (Active LOW)
X L H X HH
H L L X X B0(2)
L L L LL
L L L HH
L L L L X B0(2)
L L L H X B0(3)
NOTES:
3247 tbl 02
1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA,
LEAB
A-to-B Latch Enable Input
LEBA and CLKBA.
2. Output level before the indicated steady-state input conditions were
LEBA
B-to-A Latch Enable Input
established.
CLKAB
A-to-B Clock Input
3. Output level before the indicated steady-state input conditions were
established, provided that CLKAB was HIGH before LEAB went LOW.
CLKBA
Ax
B-to-A Clock Input
A-to-B Data Inputs or B-to-A 3-State Outputs
4. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Bx B-to-A Data Inputs or A-to-B 3-State Outputs
CLKENAB A to B Clock Enable Input
Z = High-impedance
↑ = LOW-to-HIGH Transition
CLKENBA B to A Clock Enable Input
3247 tbl 01
5.9 2


Part Number IDT74FCT16601CT
Description FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
Maker Integrated Device Technology
Total Page 7 Pages
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