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Integrated Device Technology Electronic Components Datasheet

NW6005 Datasheet

ENHANCED TYPE II CALLER ID DECODER

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ENHANCED TYPE II CALLER ID DECODER
NW6005
FEATURES
1200 baud Bell 202 and ITU-T V.23 Frequency Shift Keying
(FSK) Demodulation
Compliant with following specifications:
Bellcore GR-30-CORE & SR-TSV-002476
TIA/EIA-716, TIA/EIA-777 Draft
British Telecom (BT) SIN227 & SIN242
ETSI ETS 300 778-1 and -2
Bellcore “CPE Alerting Signal (CAS)”, British Telecom “Idle State
and Loop State Tone Alert Signal” and ETSI “Dual Tone Alerting
Signal (DT-AS)” detection
Two seperate OP amps with adjustable gain for Tip/Ring and
Telephone Hybrid connections
Monitoring of the stop bit for framing error check
Serial FSK data interface with selectable output of bit stream or 1
byte buffer
FSK carrier detection
3 V or 5 V operation
Low power CMOS with intelligent powerdown mode
Operating temperature range: -40 °C to +85 °C
Packages available:
NW6005-XS 20 pin SOIC
(where ‘X’ is the revision ID)
DESCRIPTION
The NW6005 device is a single-chip, 3/5 Volt CMOS caller ID with
call waiting detection circuit. It can receive signals following Bellcore
GR-30-CORE & SR-TSV-002476, BT SIN227 & SIN242, and ETSI
ETS 300 788-1/-2 specifications.
The NW6005 provides 1200 baud Bell 202 and ITU-T V.23 FSK
demodulation and CAS/DT-AS detection. Two seperate differential
input amplifiers allow the device to be connected with both Tip/Ring
and Telephone Hybrid receive pair. FSK demodulation is
implemented only on Tip/Ring, while DT-AS (or CAS) detection can be
on either Tip/Ring or Hybrid Receive. In addition, NW6005 provides a
serial FSK data interface via which the data can be selected to be
processed as a bit stream or extracted from a 1 byte built-in buffer.
The device can be used in feature or cordless phones for BT
Calling Line Identity Presentation (CLIP), CCA CLIP and Bellcore
Calling Identity Delivery (CID) systems. It can also be used in caller ID
boxes, modem, fax machines, answering machines, database query
systems and Computer Telephony Integration (CTI) systems.
FUNCTIONAL BLOCK DIAGRAM
OSCOUT OSCIN
CB0 CB1 CB2
VREF
IN1+
IN1-
GS1
IN2+
IN2-
GS2
Bias
Generator
PWDN
GS1EN
+
-
+
-
GS2EN
Oscillator
CASEN
Dual Tone
Detector
FSK
Demodulator
FSKEN
Control Bit
Decoder
PWDN FSKEN GS1EN
CASEN MODE
GS2EN
Guard Time
Data/Timing Recovery
MODE
ST/GT
DR/STD
EST
CD
DCLK
DATA
Figure 1. Block Diagram
The IDT logo is a registered trademark of Integrated Device Technology, Inc
INDUSTRIAL TEMPERATURE RANGE
©2002 Integrated Device Technology, Inc.
JULY 2002
DSC-6048/3


Integrated Device Technology Electronic Components Datasheet

NW6005 Datasheet

ENHANCED TYPE II CALLER ID DECODER

No Preview Available !

NW6005 ENHANCED TYPE II CALLER ID DECODER
PIN INFORMATION
VREF
IN1+
IN1-
GS1
GND
OSCIN
OSCOUT
CB0
DCLK
DATA
1
2
3
4
5
6
7
8
9
10
INDUSTRIAL TEMPERATURE RANGE
20 IN2+
19 IN2-
18 GS2
17 CB2
16 CB1
15 VCC
14 CD
13 ST/GT
12 EST
11 DR/STD
Figure 2. Pin Assignment
Name
VREF
IN1+
IN1-
GS1
GND
OSCIN
OSCOUT
CB0
DCLK
DATA
Type Pin No.
Description
O 1 Reference Voltage.
This output is used to bias the input OP amp. It is typically VCC/2.
I 2 Non-inverting Input of the gain adjustable Tip/Ring OP amp.
I 3 Inverting Input of the gain adjustable Tip/Ring OP amp.
O 4 Gain Select Output of the gain adjustable Tip/Ring OP amp.
The Tip/Ring signal can be attenuated or amplified at GS1 by adjusting the feedback resistor between GS1 and
IN1-. The FSK signal is always detected by Tip/Ring OP amp while DT-AS signal can be detected by either
Tip/Ring or Hybrid OP amp. The OP amp selection is controlled by CB1 and CB2 pins.
- 5 Ground.
I 6 Oscillator Input.
A 3.579545 MHz crystal or ceramic resonator should be connected between this pin and the OSCOUT. It can also
be driven by an external clock source.
O 7 Oscillator Output.
A 3.579545 MHz crystal or ceramic resonator should be connected between this pin and the OSCIN. When an
external clock drives OSCIN, this pin can be left floating.
I 8 Control Bit 0 (FSK Data Interface Mode Select).
This pin can select the 3-wire FSK data interface mode. A ‘0’ on this pin indicates interface mode 0; while a ‘1’ on
this pin indicates interface mode 1. (The FSK data interface is consisted of DATA, DCLK and DR/STD pins.)
When CB0 is high and CB1, CB2 are both low, the device is set into the power down state.
I/NC 9 Data Clock of the Serial FSK Interface.
In mode 0 (CB0 is low), this pin is unused; In mode 1 (CB0 is high), this pin is an input which clock the FSK data
byte out to the DATA pin.
O 10 Data Output of the Serial FSK Interface.
In mode 0 (CB0 is low), the FSK serial bit stream is output to the DATA pin directly.
In mode 1 (CB0 is high), the start bit is stripped off, the data byte and the stop bit is stored in a 9-bit buffer. At the
end of each word signaled by the DR/STD pin, the microcontroller should shift the byte out onto the DATA pin by
applying 8 read pulses to the DCLK pin. A 9th DCLK pulse will shift out the stop bit for framing error checking.
2


Part Number NW6005
Description ENHANCED TYPE II CALLER ID DECODER
Maker Integrated Device Technology
Total Page 20 Pages
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