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IS49NLC18160 - 288Mb Common I/O RLDRAM 2 Memory

Download the IS49NLC18160 datasheet PDF (IS49NLC93200 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for 288mb common i/o rldram 2 memory.

Description

1.1 288Mb (32Mx9) Common I/O BGA Ball-out (Top View) 1 A VREF B VDD C VTT D A221 E A212 F A5 G A8 H BA2 J NF3 K DK L REF# M WE# N A18 P A15 R VSS T VTT U VDD V VREF 2 VSS DNU4 DNU4 DNU4 DNU4 DNU4 A6 A9 NF3 DK# CS# A16 DNU4 DNU4 DNU4 DNU4 DNU4 ZQ 3 VEXT DNU4 DNU4 DNU4

Features

  • 400MHz DDR operation (800Mb/s/pin data rate).
  • 28.8Gb/s peak bandwidth (x36 at 400 MHz clock frequency).
  • Reduced cycle time (15ns at 400MHz).
  • 32ms refresh (8K refresh for each bank; 64K refresh command must be issued in total each 32ms).
  • 8 internal banks.
  • Non-multiplexed addresses (address multiplexing option available).
  • SRAM-type interface.
  • Programmable READ latency (RL), row cycle time, and burst sequence length.
  • Balanced READ and WRITE latencies in.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS49NLC93200-IntegratedSiliconSolution.pdf) that lists specifications for multiple related part numbers.

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Full PDF Text Transcription

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IS49NLC93200,IS49NLC18160,IS49NLC36800 288Mb (x9, x18, x36) Common I/O RLDRAM 2 Memory JANUARY 2020 FEATURES  400MHz DDR operation (800Mb/s/pin data rate)  28.8Gb/s peak bandwidth (x36 at 400 MHz clock frequency)  Reduced cycle time (15ns at 400MHz)  32ms refresh (8K refresh for each bank; 64K refresh command must be issued in total each 32ms)  8 internal banks  Non-multiplexed addresses (address multiplexing option available)  SRAM-type interface  Programmable READ latency (RL), row cycle time, and burst sequence length  Balanced READ and WRITE latencies in order to optimize data bus utilization  Data mask signals (DM) to mask signal of WRITE data; DM is sampled on both edges of DK.
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