IS61DDB42M18 Datasheet DDR-II (Burst of 4) CIO Synchronous SRAMs

Manufacturer: ISSI (now Infineon)

Datasheet Details

Part number	IS61DDB42M18
Manufacturer	ISSI (now Infineon)
File Size	512.68 KB
Description	DDR-II (Burst of 4) CIO Synchronous SRAMs
Download	IS61DDB42M18 Download (PDF)

The 36Mb IS61DDB41M36 and IS61DDB42M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have a common I/O bus.

The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.

36 Mb (1M x 36.

& 2M x 18) ISSIDDR-II (Burst of 4) CIO Synchronous SRAMs.

1M x 36 or 2M x 18.
On-chip delay-locked loop (DLL) for wide data valid window.
Common I/O read and write ports.
Synchronous pipeline read with late write operation.
Double data rate (DDR-II) interface for read and write input ports.
Fixed 4-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K) for address and control registering at rising edges only.
Two input clocks (C an.

Part Number	Description
IS61DDB42M18A	36Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB42M36	DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61DDB42M36A	72Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB41M18A	18Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB41M36	DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61DDB41M36A	36Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB44M18	DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61DDB44M18A	72Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB451236A	18Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB21M18A	18Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM