IS61DDP2B44M18A2 sram equivalent, 72mb ddr-iip cio synchronous sram.
DESCRIPTION
* 2Mx36 and 4Mx18 configuration available.
* On-chip Delay-Locked Loop (DLL) for wide data
valid window.
* Common I/O read and write ports.
.
where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system o.
* 2Mx36 and 4Mx18 configuration available.
* On-chip Delay-Locked Loop (DLL) for wide data
valid window.
* Common I/O read and write ports.
* Synchronous pipeline read with self-timed late write
operation.
* Double Data Rate (DDR.
Image gallery
Download