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IS61LF6432A - SYNCHRONOUS FLOW-THROUGH STATIC RAM

Description

low-power synchronous static RAM designed to provide a burstable, high-performance, memory.

IS61LF6432A is organized as 65,536 words by 32 bits.

IS61LF6436A is organized as 65,536 words by 36 bits.

Features

  • Internal self-timed write cycle.
  • Individual Byte Write Control and Global Write.
  • Clock controlled, registered address, data and control.
  • Interleaved or linear burst sequence control us- ing MODE input.
  • Three chip enables for simple depth expansion and address pipelining.
  • Common data inputs and data outputs.
  • Power-down control by ZZ input.
  • JEDEC 100-Pin TQFP package.
  • Power Supply: +3.3V Vdd +3.3V or 2.5V Vddq.

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📁 Similar Datasheet

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IS61LF12832EC SYNCHRONOUS FLOW-THROUGH SRAM ISSI
IS61LF12836A (IS6xxFxxxxxA) Synchronous Flow-through Static RAM ISSI
IS61LF12836EC SYNCHRONOUS FLOW-THROUGH SRAM ISSI

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61LF6436A SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61LF25636A 256K x 36-512K x 18 9Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61LF51218A 256K x 36-512K x 18 9Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61LP6432A 64K x 32 or 64K x 36 SYNCHRONOUS PIPELINED STATIC RAM
IS61LP6432A 64K x 32- 64K x 36 SYNCHRONOUS PIPELINED STATIC RAM

Full PDF Text Transcription

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IS61LF6436A IS61LF6432A ® Long-term Support World Class Quality 64Kx32, 64Kx36 SYNCHRONOUS FLOW-THROUGH STATIC RAM MAY 2017 FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control us- ing MODE input • Three chip enables for simple depth expansion and address pipelining • Common data inputs and data outputs • Power-down control by ZZ input • JEDEC 100-Pin TQFP package • Power Supply: +3.3V Vdd +3.3V or 2.
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