IS61LPD102418A - 512K x 36 - 1024K x 18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM

Integrated Silicon Solution

The IS61LPD102418A by Integrated Silicon Solution is a 512K x 36 - 1024K x 18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM. Below is the official datasheet preview.

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IS61LPD102418A 512K x 36 - 1024K x 18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM by Integrated Silicon Solution - Datasheet Preview — Official preview page of the **IS61LPD102418A** 512K x 36 - 1024K x 18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM datasheet (Integrated Silicon Solution).

Datasheet Details

Part number	IS61LPD102418A
Manufacturer	Integrated Silicon Solution
File Size	251.04 KB
Description	512K x 36 - 1024K x 18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM
Datasheet	IS61LPD102418A_IntegratedSiliconSolution.pdf
Additional preview pages of the IS61LPD102418A datasheet.

IS61LPD102418A Product details

Description

The ISSI IS61LPD/VPD51236A and IS61LPD/ VPD102418A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications.The IS61LPD/VPD51236A is organized as 524,288 words by 36 bits, and the IS61LPD/VPD102418A is organized as 1,048,576 words by 18 bits.Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a singl

Features

Internal self-timed write cycle.
Individual Byte Write Control and Global Write.
Clock controlled, registered address, data and control.
Burst sequence control using MODE input.
Three chip enable option for simple depth expansion and address pipelining.
Common data inputs and data outputs.
Auto Power-down during deselect.
Double cycle deselect.
Snooze MODE for reduced-power standby.
JTAG Boundary Scan for.

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Other Datasheets by Integrated Silicon Solution

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Published: Apr 17, 2010 |