IS61LPS25618A Datasheet | ISSI

IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A 128K x 32, 128K x 36, 256K x 18 DECEMBER 2013 4 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM Features - Internal self-timed write cycle - Individual Byte Write Control and Global Write - Clock controlled, registered address, data and control - Burst sequence control using MODE input - Three chip enable option for simple depth ex- pansion and address pipelining - mon data inputs and data outputs - Auto Power-down during deselect - Single cycle deselect - Snooze MODE for reduced-power standby - Power Supply LPS: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5% VPS: Vdd 2.5V + 5%, Vddq 2.5V + 5% - JEDEC 100-Pin QFP, 119-ball and 165-ball BGA packages - Automotive temperature available - Lead Free available FAST ACCESS TIME Symbol Parameter tkq Clock Access Time tkc Cycle Time Frequency DESCRIPTION The  ISSI IS61(64)LPS12832A, IS61(64)LPS/VP- S12836A and IS61(64)LPS/VPS25618A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for munication and networking applications.The IS61(64)LPS12832A is organized as 131,072 words by 32 bits.The IS61(64)LPS/ VPS12836A is organized as 131,072 words by 36 bits. The IS61(64)LPS/VPS25618A is organized as 262,144 words by 18 bits.Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit.All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input.Write cycles can be one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. The byte write operation is performed by using the byte write enable (BWE) input bined with one or more individual byte...