IS61NLP409618B sram equivalent, pipeline (no wait) state bus sram.
* 100 percent bus utilization
* No wait cycles between Read and Write
* Internal self-timed write cycle
* Individual Byte Write Control
* Single R/W .
They are organized as 2,096,952 words by 36 bits and 4,193,904 words by 18
bits, fabricated with ISSI's advanced CMOS t.
Image gallery
Download