IS61VF51218A - 256K x 36-512K x 18 9Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
ISSI (now Infineon)
Download the IS61VF51218A datasheet PDF.
This datasheet also covers the IS61LF25636A variant, as both devices belong to the same 256k x 36-512k x 18 9mb synchronous flow-through static ram family and are provided as variant models within a single manufacturer datasheet.
General Description
high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications.
The IS61LF/ VF25636A is organized as 262,144 words by 36 bits.
Key Features
Internal self-timed write cycle.
Individual Byte Write Control and Global Write.
Clock controlled, registered address, data and control.
Burst sequence control using MODE input.
Three chip enable option for simple depth expansion and address pipelining.
Note: The manufacturer provides a single datasheet file (IS61LF25636A_IntegratedSiliconSolution.pdf) that lists specifications for multiple related part numbers.
Full PDF Text Transcription for IS61VF51218A (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
IS61VF51218A. For precise diagrams, and layout, please refer to the original PDF.
IS61LF25636A IS61LF51218A IS61VF25636A IS61VF51218A www.DataSheet4U.com ISSI MAY 2005 ® 256K x 36, 512K x 18 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal ...
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12K x 18 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs and data outputs • Auto Power-down during deselect • Single cycle deselect • Snooze MODE for reduced-power standby • JTAG Boundary Scan for PBGA package • Power Supply LF: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5% VF: VDD 2.5V + 5%, VDDQ 2.
IS61VF51218A Datasheet
