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IS61VPD102418A - 512K x 36/ 1024K x 18 18Mb SYNCHRONOUS PIPELINED / DOUBLE CYCLE DESELECT STATIC RAM

Download the IS61VPD102418A datasheet PDF. This datasheet also covers the IS61LPD102418A variant, as both devices belong to the same 512k x 36/ 1024k x 18 18mb synchronous pipelined / double cycle deselect static ram family and are provided as variant models within a single manufacturer datasheet.

General Description

VPD102418A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications.

Key Features

  • Internal self-timed write cycle.
  • Individual Byte Write Control and Global Write.
  • Clock controlled, registered address, data and control.
  • Burst sequence control using MODE input.
  • Three chip enable option for simple depth expansion and address pipelining.
  • Common data inputs and data outputs.
  • Auto Power-down during deselect.
  • Double cycle deselect.
  • Snooze MODE for reduced-power standby.
  • JTAG Boundary Scan for.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61LPD102418A_IntegratedSiliconSolution.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number IS61VPD102418A
Manufacturer ISSI (now Infineon)
File Size 251.04 KB
Description 512K x 36/ 1024K x 18 18Mb SYNCHRONOUS PIPELINED / DOUBLE CYCLE DESELECT STATIC RAM
Datasheet download datasheet IS61VPD102418A Datasheet

Full PDF Text Transcription for IS61VPD102418A (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for IS61VPD102418A. For precise diagrams, and layout, please refer to the original PDF.

IS61VPD51236A IS61VPD102418A IS61LPD51236A IS61LPD102418A 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM www.DataSheet4U.com ISSI ® FE...

View more extracted text
ELINED, DOUBLE CYCLE DESELECT STATIC RAM www.DataSheet4U.com ISSI ® FEBRUARY 2006 FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs and data outputs • Auto Power-down during deselect • Double cycle deselect • Snooze MODE for reduced-power standby • JTAG Boundary Scan for PBGA package • Power Supply LPD: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5% VPD: VDD 2.5V + 5%, VDDQ 2.

More Datasheets from ISSI (now Infineon)

Part Number Description
IS61VPD102418A 512K x 36 - 1024K x 18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM
IS61VPD25636A 256K x 36 - 512K x 18 9 Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM
IS61VPD25636A 256K x 36/ 512K x 18 9Mb SYNCHRONOUS PIPELINED / DOUBLE CYCLE DESELECT STATIC RAM
IS61VPD51218A 256K x 36 - 512K x 18 9 Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM
IS61VPD51218A 256K x 36/ 512K x 18 9Mb SYNCHRONOUS PIPELINED / DOUBLE CYCLE DESELECT STATIC RAM
IS61VPD51236A 512K x 36 - 1024K x 18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM
IS61VPD51236A 512K x 36/ 1024K x 18 18Mb SYNCHRONOUS PIPELINED / DOUBLE CYCLE DESELECT STATIC RAM
IS61VPS102418A 18Mb Single CYCLE DESELECT STATIC RAM
IS61VPS102418B SINGLE CYCLE DESELECT STATIC RAM
IS61VPS102436A 36Mb Single CYCLE DESELECT STATIC RAM