* Internal self-timed write cycle
* Individual Byte Write Control and Global Write
* Clock controlled, registered address, data and control
* Burst sequence control using MODE input
* Three chip enable option for simple depth ex- pansion and address pipelini
IS61VPS204818A Datasheet (385.02 KB)
IS61VPS204818A
Integrated Silicon Solution
385.02 KB
36mb single cycle deselect static ram.
IS61vPS102436A IS61lPS102436A IS61vPS204818A IS61lPS204818A 1Mb x 36, 2Mb x 18 36Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM JUNE 2010.
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