* Internal self-timed write cycle
* Individual Byte Write Control and Global Write
* Clock controlled, registered address, data and control
* Burst sequence control using MODE input
* Three chip enable option for simple depth ex- pansion and address pipelini
IS61VPS25672A Datasheet (614.98 KB)
IS61VPS25672A
Integrated Silicon Solution
614.98 KB
18mb single cycle deselect static ram.
IS61vPS25672A IS61lPS25672A IS61vPS51236A IS61lPS51236A IS61vPS102418A IS61lPS102418A 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, Sin.
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