or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilitie.

64-Bit Interunit Transfer Bus 32-Bit Data Bus 32-Bit Data Bus Linear Address 32 32 32 PCD PWT Core Clock Clock Contr.

at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for confl.

80486

80486DX

80486DX2RP

8048AH

8040

80401-NW

8040AHL

8041-05-011

8041-05-xxx

8041-12-xxx

8041AH

8042AH

8044AH